Reference Shipboard MVDC Architecture

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Proposed MVDC Small Signal Stabilizer

This thesis designs a negative load virtual small signal stabilizer in a uni-directional PCM for a shipboard MVDC system to support pulsed loads. The ES will be used to cancel out the stabilizer’s power fluctuations on the downstream load. This stabilizer should guarantee small signal stability across a wide power range seen in pulsed loads. Because pulsed loads will greatly change its equivalent load resistance on the MVDC bus, this thesis proposes to dynamically tune the virtual stabilizer with the load power consumption. To implement the stabilizer, a working MVDC model needs to be developed. Also, control loops must be made for the various functions of the PCM. From there, a small signal stability criteria needs to be developed. Finally, method of tuning the stabilizer to be stable is needed.

Simplified MVDC Model

As mentioned before, the reference MVDC model is fairly complex. For the sake of developing and testing a this negative load stabilizer design, the MVDC system model has been simplified into what is shown in Fig. 4.1. This model has a single ideal generator with voltage droop. There is a generic reference design PCM which has an internal DC bus with a bus capacitor, internal ES, and the downstream constant power load. Each of the DC/DC power converters within the PCM have power and power ramp rate limitations and follow the power flow of a reference PCM-1A. The is a RLC component that is a simplified representation of the electrical characteristics of a generator, power converter with filter, and MVDC bus as discussed in Section 2.2.4. This was done assuming that the system could be represented as such done in [12]. This model can be converted to a more complex model by: separating out the electrical characteristics, expanding the power converter with input filter values and switching, and/or add a parallel PCM on the MVDC bus. Without the virtual stabilizer in the simplified circuit, the small signal stability criteria is where P is the power consumption of the PCM from the MVDC bus, V_MVDC is the MVDC bus voltage at the PCM, and R, L, and C are the RLC characteristics of the MVDC bus. Note that V_MVDC may fluctuate due to noise or voltage droop, and P will also change drastically during power pulsing. Therefore, the above small signal stability criteria must considered for all operating points.

Control Loops

A set of control loops were developed to control the PCM’s internal behavior and interactions with the MVDC bus. The controller maintains the internal bus voltage while allowing the virtual stabilizer to inject power on its MVDC input power converter. Also, the controller manages and utilizes the ES while ensuring power quality to the downstream constant power load. The ES control loop uses the ES for internal bus regulation while the MVDC side power converter control loop attempts to balance power consumption with power sourced from the MVDC bus. A number of the following control loops used in this thesis were adapted from other papers. Besides the virtual stabilizer control loop, the PCM control loops were adapted from [6]. These control loops were intended for a zonal DC bus with a generator, ES, PCM power input from an MVDC bus, and CPL. These control loops were not tested with pulsed power loads. The MVDC bus to PCM internal DC bus DC/DC power converter control loop adapted from [6] is shown in Fig. 4.2. The control loop’s i_G0 has been removed as there is no generator inside the reference PCM design. Also, the controls delay transfer functions have been removed to simplify the model. The modified MVDC side power converter controls loop used in this thesis is shown in Fig. i_L is the CPL’s current at the internal bus voltage V_IBus. ¯i_ES is the set ES recharge current at V_IBus. i_CV is the current of the virtual stabilizing capacitor at V_IBus. dt^d i′_PGM is a virtual ramp rate limit on the MVDC side power converter. This represents the equivalent MVDC bus generator’s power ramp rate limitations as a current at V_IBus, and loads should not exceed the generator’s ramp rate limits. i_PCM and _dt^d i_PCM are the actual current and ramp rate limits of the MVDC side power converter at V_IBus. The extra ramp rate was applied because the virtual capacitor is not a ”real” load, and does not obey the generator limits to provide stabilization services. However, the PCM is implementing the virtual stabilizer and must obey its own limitations. For the virtual capacitor stabilizer, the power of the virtual capacitor is The virtual capacitor stabilizer control loop was adapted from , and it is recreated below in Fig.There is low-pass filter in this control loop that was implemented by subtracting the output of a high-pass filter from the original signal. Did not explicitly state that there was an added virtual resistance, but there is one due to the nature of the low pass filter in the control loop. This thesis converted the control loop’s virtual capacitor’s power P_VC to the virtual capacitor’s, or stabilizer’s, current i_VC at V_IBus. Hardware limits were also incorporated on the virtual capacitor. These limits were applied because the converter hardware cannot completely replicate a real RC stabilizer behavior, and the control loop should reflect this. Also, the low-pass filter configuration was simplified in this thesis’s control loop into a transfer function based on the virtual resistor R_V and capacitor C_V values. PCM hardware limits were applied to the virutal capacitor, because the PCM is emulating the ”real” equivalent hardware. As stated before, the ramp rate limit  is a virtual limit to follow an MVDC bus generator’s ramp rate limits. The virtual stabilizer is not a ”real” load, and it must function as closely to a real stabilizer to provide stabilization. Therefore, the generator’s ramp rates were ignored and the PCM’s ramp rate limits were used instead. Furthermore, the PCM’s power limits were applied in plus-minus form as the stabilizer can only change PCM power to zero at full PCM power or to full power at no PCM power. Later on in the PCM’s control block, the i_CV term will be added up and have the PCM’s ramp rate and power limitations re-applied to ensure all of the PCM’s limitations are obeyed. The ES control loop has been modified from [6], with the original control loop replicated in Fig. Used a simple proportional controller for internal bus voltage regulation. The ES that was used had infinite energy, and the injected i_E0 is to manually set the current contributed by the ES. Finally, a control delay transfer function as added at the end. V is the current bus voltage and V ∗ is the nominal bus voltage. This thesis removes the controls delay and adds current ramp rate and saturation limits. Because the ES must be at or near its nominal energy level whenever possible to provide hold-up power at any time, this thesis assigns finite energy capacity to the ES. The modified ES bus voltage regulation control loop is shown in Fig. with an additional ES control loop to return to nominal SoC shown in Fig. The original V and V ∗ have been replaced with V_IBus and V_IBus∗ to represent that the regulated bus voltage is specifically the PCM’s internal DC bus. ¯i_ES represents the ES nominal energy regulator control loop output from Fig. 4.8. i_CV represents the current of the virtual capacitor stabilizer at V_IBus as the ES will need to cancel out the power fluctuations of the virtual stabilizer to maintain power quality. Finally,and i_ES ramp rate and saturation limits were applied to represent the physical power limitations of the ES hardware. The proportional controller was replaced with a proportional-integral controller. The integral term is required for pulsed loads. This is because the internal DC bus voltage will sag from aggressive load power consumption ramp rates. With only the proportional term, the voltage sag will only grow worse as the CPL current will increase upon voltage sag, overpowering the error correction of the proportional only controller. If the proportional controller’s coefficient K_P is very high to compensate for voltage sag, the internal DC bus voltage will become unstable. V_IBUS will oscillate and grow away from V_IBUS∗ and never converge. The integral term corrects the voltage sag over time with even more current, preventing the increased CPL current from collapsing the bus voltage. The integral term removes the need of a high K_P, preventing the proportional term from becoming unstable. Since the ES is finite, an ES energy management control loop was developed and shown in Fig E_ES is the current ES energy. E_ES∗is the nominal energy that the ES should normally stay at. The ES should not destabilize the DC buses and obey the generator limits when recharging or discharging to nominal E_ES∗ , so the ES energy regulation is limited by the MVDC generator’s ramp rate limits and PCM’s current limits. The ES will also never attempt to return to nominal energy levels when the internal bus voltage V_IBus is not within its tolerances Tol as the ES’s first role is to regulate the internal DC bus voltage. A proportional controller was used to return the ES to its nominal SoC, allowing a more aggressive charge/discharge the further E_ES is from E_ES∗ . The proportional controller’s coefficient K_R must be large enough so that the ES will return to nominal SoC fast enough, but it cannot be too large where the SoC E_ES will not stably converge towards E_ES∗ . The K_R term must follow the criteria . This is because E_ES∗ and E_ES are in units of Joules of energy, and the output of this control loop i_ES¯ is in units of current at V_IBUS. With K_R = 1, V_IBUS of power will be used to charge/discharge 1J of energy difference between E_ES and E_ES∗ . If V_IBUS > 1, E_ES would overshoot and never converge to E_ES∗ as >1W is used to charge/discharge the 1J error. Since V_IBUS may fluctuate, a safety margin on K_R is required.

Voltage Droop

Voltage droop is useful for current sharing of parallel generators or power converters [11]. Therefore, it is important to allow the MVDC bus voltage to quickly settle. To allow this, the stabilizer must avoid overly over-damping the system, which can be a dynamic tuning criteria. The voltage droop used in this model is defined as where V_NL is the voltage droop at no load on the generators, V_FL is the voltage droop at full load on the generators, i_PGM is the current generator output current, and i_PGMMax is the max output current of the generator. The ratio of all generators in the system should be equal when the generators are balanced via voltage droop.

Controls Bandwidth

Controls bandwidth is important to keep in mind to ensure that this proposed small signal virtual stabilizer is realistically feasible. The controller cannot actuate a real power converter faster than the power converter’s switching speed. At maximum, the controller has a maximum operating frequency of half the converter’s switching frequency. Ideally, the controller should operate at most  the converter’s switching frequency. The virtual C_V and R_V should result in an operating bandwidth of no more than  of the converter’s switching frequency, too. This is so that the converter is capable of generating a power waveform mimicking a real RC stabilizer’s waveform. Silicon carbide power converters for MVDC applications are being developed, and they have higher switching frequencies than their traditional silicon-only power electronics . With silicon carbide power converters, the switching frequency can be in the range of tens of kHz for MVDC applications .

Equivalent Circuit

The simplified MVDC system shown in Fig. 4.1 can be simplified into a system of equivalent passive components. The R_V and C_V represents the virtual stabilizer implemented in the PCM’s controls. The R_L is the equivalent resistance of the PCM as a CPL at a set voltage and power draw. Though the PCM has internal ES, if the downstream CPL of the PCM is not ramped faster than the generator’s ramp rate limits of, then the R_L will accurately represent the downstream CPL itself as the PCM ES will not compensate for any generator power mismatch.

Transfer Function

Using the equivalent circuit representation of the MVDC system, a 3^rd order transfer function can be derived. CPLs act and can be modeled as a negative resistor . Therefore, for accurate modeling, R_L is negative when calculating the transfer function. The transfer function of the equivalent circuit is a desired MVDC damping factor ζ, low-Q approximation was used.

Low-Q Approximation

Low-Q approximation allows order reduction of polynomials into their approximate 1^st and 2^nd order roots. In the equivalent circuit’s use case, the polynomial is the transfer function’s poles (denominator). This makes it possible to reasonably approximate the roots of high order transfer functions. However, the roots must be real and well separated for low-Q approximation to be accurate . The further the roots are separated results in a more accurate approximation. shows the original mathematical proof for 2^nd order polynomials, and  has expanded low-Q approximation to a more general case to support higher than 2^nd order polynomials. Has also defined special cases where only two roots are close together. The close together roots can remain in quadratic form while the other roots are in 1^st order form. Only quadratic roots were covered by , but it is theoretically possible to keep roots in higher order (e.g. cubic) forms if more than 2 roots are close together. This section will only provide the lowQ approximation methodology and formulation for the transfer function Eq. for the model in Fig but more information can be found about the general low-Q approximation methodology in First, the inequalities used in low-Q approximation are defined using significant inequalities (≫ and ≪). Let the term α represent how significant the inequality is. Therefore, if a ≫ b, then aα > b. This value is important for low-Q approximation as a smaller α means that the roots are further separated and results in a more accurate approximation . With a more accurate approximation, the correctness of the stabilizer is greater, so it is important to record how accurate the low-Q approximation was done.

1. Introduction
1.1 Contributions
2. Review of Literature
2.1 All Electric Ship Power Systems
2.2 Reference Shipboard MVDC Architecture
2.3 Negative Load Virtual Stabilization
3. Pulsed Power Loads
3.1 Implementing a Controller for a Pulsed Load Prototype
4. Proposed MVDC Small Signal Stabilizer
4.1 Simplified MVDC Model
4.2 Control Loops
4.3 Low-Q Approximation
5. Theory Verification
5.1 Small Signal Stability Criteria
5.2 Equivalent Circuit Validation
5.3 Transfer Function Validation
5.4 Low-Q Approximation Validation
5.5 Dynamic Tuning Validation
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