SOI Wafers and CMOS SOI Process Technologies

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MOSFET downscaling and evolution

In this paragraph we will present a brief overview of the history of microelectronics. We will continue with the challenges faced during the miniaturization process as well as the current solutions to overcome them. Future device trends will be presented with an emphasis on the type of structures that resemble our own work.
In 1930 Julius Edgar Lilienfeld filed a patent for a semiconductor transistor based on a film of copper sulphur compound [1], while in 1947 Bardeen, Brattain [2] and Shockley [3] built the first bipolar transistors. Integrated silicon circuits first appeared in 1958 [4], and the MOSFET in 1960 [5]. Thus two of the most popular devices for logic applications were born. Over the years the use of them diversified: Bipolar transistors are easier to manufacture, offer low input impedance and are more linear than MOSFETs. They dominated the field of analog electronics, specifically as amplification elements. MOSFETs on the other hand, with their high input impedance and switching characteristics, prevailed in the digital market. In 1965 the magazine Electronics presented a forecast by Gordon Moore on the development of integrated circuits [6]. According to this prediction (now known as the Moore’s Law), the number of transistors per chip double every year and this would continue for at least ten years. The next important milestone in the evolution of Microelectronics was the invention of the Complementary Metal Oxide Semiconductor (CMOS) logic by Wanlass in 1967 [7]. Finally the emergence of Very Large Scale Integration (VLSI) in 1980 with typical values of 105 transistors per chip boosted the industry and created today’s 300 billion dollar market [8].
Although Moore’s Law was valid in general and without special changes, the projected rate (doubling every year, Fig.1.1) changed in the mid-1970s, with a doubling of transistors per chip every 2 years and for more than 30 years the density of devices continued under this exponential growth. This prediction was updated more than once, additionally taking into account different technologies used for memory elements compared to logic functions (Fig. 1.2). But what is the benefit of this continuous miniaturization? The answer to this question is mainly the cost. The ongoing miniaturization leads to cost reduction per integrated circuit, and thus drops the cost per logic function (Fig. 1.3). The reduction of the silicon surface occupied by the circuit leads to more functions on the same area. This scaling trend reduces at the same time the operating voltage and allows operation with lower power consumption.
The advantages exhibited by the continuously smaller circuits led to a flourishing of microelectronics industry since the early 70s’ with digital systems and particularly microprocessors mainly driving this advancement. This very rapid development created the need for deeper understanding of the natural phenomena that manifest in the micro and nano-scale. Understanding the manufacturing challenges and operational limits of such devices is critical to the continuation of this technology growth. In order to monitor these activities the NTRS (National Technology Roadmap for Semiconductors) was established in 1990 in the US, which was later replaced by the ITRS (International Technology Roadmap for Semiconductors. The current edition of the ITRS is the version of 2015. The ITRS objective is to answer the question; « What techniques are needed to be developed by the industry in order to continue to apply the Moore’s Law?”[9].
Continued miniaturization reveals new technological difficulties and physical limitations along with the benefits of reduced dimensions. Silicon based technology has prevailed due to the smaller power consumption of CMOS compared to competitive architectures, and because it is possible to process high quality silicon and SiO2 crystal structures. The need for good electrostatic control over the channel area, has led to very thin gate oxides that through direct or Fowler-Nordheim tunneling can increase the leakage currents. This can negatively affect the low power consumption advantage of CMOS. With polysilicon gate electrodes, Boron penetration into the channel area can change the subthreshold slope of the device and the device becomes normally on. The shrinking of gate length degrades the device performance due to short channel effects:
Drain-induced barrier lowering [10], can reduce the threshold voltage (VTH) for higher drain voltages since the electrostatic control of the gate is lost due to the small barrier width (Fig. 1.4).
Velocity saturation [11] occurs when a strong electric field is applied and the carrier reaches a maximum velocity known as saturation velocity (vSAT). Increasing the electric field ceases to control the carrier velocity since carriers collide with the crystal lattice and lose their extra energy.
Impact ionization [12], [13] occurs at high electric field and high energy carriers create new electron-hole pairs. This can result in avalanche breakdown that generates very high currents.
Hot carrier injection, (HCI) [14]–[16] occurs when carriers with high energy overcome the potential barrier and enter the gate dielectric, increasing leakage currents and defects (Fig. 1.4). Some of these effects will be described in detail since they can seriously affect the behavior of our devices on the nanometer scale.
Fig. 1.4: DIBL effect showing potential distribution along the channel [10] (left), HCI effect demonstrating the electron injection inside the oxide [14] (right).
Despite the above problems, the continued miniaturization is necessary and this trend is referred to as More Moore. Specifically, the More Moore trend dictates:
1) The miniaturization of vertical and horizontal feature sizes in order to improve the density, performance and reliability.
2) Equivalent miniaturization leading to geometric factor shrinking new fabrication processes or new materials that affect the electrical behavior of the devices.
We can see some of the challenges presented in Fig. 1.5 for regular type of MOSFETs. Gate stack is very important since the materials used need to be selected carefully in order to reduce leakage currents arising from very thin oxide formation while maintaining a low Equivalent Oxide Thickness (EOT). The gate needs to provide high capacitance and a strong vertical electric field is required to reduce VTH and decrease power supply (VDD). The solution to this is High-K Metal Gate technology which increases the capacitance while decreasing the tunneling current. The low-field mobility of the MOSFET is dependent on the channel materials, as well as on the doping. Thus, materials that enhance the mobility without any significant need to change the process are investigated, such as stressed silicon or SiGe alloys. Furthermore the increasing need for good electrostatic control by the gate, leads to recent device structures such as Fully Depleted SOI (FD-SOI), Gate All Around (GAA) or FinFETs.
For the implementation of More than Moore strategy, a wide range of devices exist, some of which are presented below (Table 1.1). The Table 1.1 focuses on emerging technologies in the field of logic devices. The devices presented are divided into different categories, depending on the state variable used to operate as well as the materials used. The main difference between them, except their physical operation mechanisms, is their ability of integration and their compatibility with existing fabrication processes. For industrial purposes this is a major factor. Research type devices with exceptional performance can be fabricated but if the industrial standards for reliability yield and variability cannot be reached the devices cease to be of interest for application. In our study we are focusing on conventional charge based devices: Si-FET, TFET, SiGe-FET as well as bipolar based devices, expanding the table with new novel structures.

SOI Technology

Within this paragraph we will give a general overview of most aspects of SOI technology. We will present the fabrication processes used and we will focus the analysis on the behavior of a typical MOSFET. More detailed analysis of the structures we investigated will be presented in the relevant chapters.

Introduction to SOI

Historically, MOSFETs as well as bipolar transistors were fabricated in silicon wafers with a thickness of some hundred micrometers. Only the top of this pure silicon material is used to fabricate the devices while the rest of the wafer leads to a number of parasitic effects that can negatively affect the device behavior. On the other hand, devices built on SOI wafers achieve better characteristics by mitigating these undesirable effects. To better understand the benefits of SOI structures we can provide the example of an inverter built with both technologies and compare its behavior.
We can observe (Fig. 1.6) the number of parasitic elements present in bulk-Si structures: capacitances between the implanted N+ or P+ regions with their respective wells, parasitic bipolar transistors forming between the n/pMOSFETs, leakage currents between the different implanted areas. On the contrary, in SOI structures these effects are blocked, and the only parasitic element is the capacitance due the buried oxide. As we will see later, the process of fabricating structures on SOI wafers is simpler and less expensive, while suppressing some yield hazard factors. Additionally SOI structures offer superior performance under radiation, mitigating Single Event Effects as well as Total Ionizing Dose effects, by effectively isolating the transistors via BOX and swallow trench isolation, STI.

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SOI Wafers and CMOS SOI Process Technologies

The process of fabricating high quality SOI wafers is paramount to the SOI process technology. The challenge is to produce a single crystal silicon film on top of a high quality silicon dioxide layer across the whole wafer area. Many techniques have been developed to address this problem:
Epitaxial growth of silicon on a wafer covered by insulated material. Polysilicon crystallization techniques, by melt and regrowth.
Creating an insulating layer inside a bulk silicon wafer thus isolating the silicon film.
The latest type of approach and now industry standard is the layer transfer technique such as Smart-Cut® (Fig.1.7) used by SOITEC®.
This last technique offers several advantages compared to the other SOI wafer fabrication methods:
i. The thickness of the transfer layer can be adjusted with high precision by adjusting the implantation energy.
ii. Very low amount of defects are left on the transferred layer.
iii. Good uniformity of thickness through the whole wafer via implantation control.
The CMOS process technology for SOI is similar to bulk albeit more simple. Transistors are formed on thick (PD-SOI) or thin (FD-SOI) silicon film that lies on top of the Buried Oxide. There is no need for well doping since the thin silicon film can be lightly doped or undoped. HALO doping is avoided except in PD-SOI. Additionally transistor isolation can be achieved by Local isolation Of Silicon (LOCOS), Mesa isolation technique or Swallow Trench Isolation (STI). In PD-SOI devices with silicon film thick enough (tSI>80nm) two implants can be implemented for adjusting the properties of front and back interface separately. In case of thin films this is not possible since any type of implant results on acquiring only the central part of the Gaussian distribution of doping. The formation of source and drain areas is similar to bulk technology with some additional concerns regarding the series resistances. The source and drain sheet resistance increases as the silicon film thickness is decreasing so methodologies to reduce it have been implemented. Using silicides like TiSi2 or CoSi2 on source/drain areas can significantly reduce the series resistance. Additionally another technique exists where source and drain areas can be raised, either through epitaxial growth or by using thicker silicon film and thinning the channel area by means of LOCOS. Tungsten can be additionally deposited on top of source/drain areas featuring an even lower sheet resistance than silicides. The gate stack in SOI technology is similar to the one in bulk, with the more advanced nodes utilizing High-K Metal Gate technology, as mentioned before.

SOI MOSFET Characterization

There are many techniques to characterize a MOSFET. Some of these techniques are used to extract physical or electrical parameters. Since full access to the process was provided the latter type of characterization is of most interest. It was the first time all of the devices presented here were fabricated and no previous work existed, hence most of the work is focused on simple type of measurements for the most important phenomena and parameters of SOI MOSFETs. Future work could continue the characterization of these novel structures by additional electrical analysis including noise, frequency and full variability analysis.
One of the most important intrinsic effects of the SOI technology is the floating body effect. A film build-up charge can be trapped inside a typical SOI MOSFET and, due to the lack of contact to the body it cannot be rapidly evacuated. This can cause a number of parasitic effects. In PD-SOI an abrupt increase in the saturation current can be observed while the interface is in the strong inversion region. This is due to impact ionization that generates electron-hole pairs inside the device. While electrons are collected to the drain, holes travel towards the source increasing the charge inside the body. In FD-SOI the behavior is expected to be different since the source-body potential barrier is smaller. On the other hand, the high lateral electric field observed in ultra-thin silicon film as well as the recombination into the small silicon volume may lead to different behavior. Further investigation of this effect will be performed in the next chapter. Additionally it is possible during weak inversion of the interface and for high drain voltages, to acquire S-shaped ID(VG) characteristics. This can create a hysteresis-like effect on the measurements while the electrostatic control provided by the gate is lost. The effect is called single transistor latch.
Fig. 1.9: Front-channel and back-channel threshold voltages versus opposite-gate bias measured in accumulation-mode SIMOX MOSFETs with various thicknesses [25]. The straight vertical lines show the limits of electrostatic threshold modulation – after a biasing value the front and back VTH cannot be modulated.
As we have seen previously with the Lim-Fossum model on FD-SOI MOSFETs, the threshold voltage is a function of backplane biasing. This effect can be summarized in the Figure 1.9.
There is a number of methods to extract critical parameters of a MOSFET structure such as threshold voltage, transconductance, low-field mobility, effective mobility as well as series resistance.

Table of contents :

Chapter 1: Introduction
1.1 MOSFET downscaling and evolution
1.2 SOI Technology
1.2.1 Introduction to SOI
1.2.2 SOI Wafers and CMOS SOI Process Technologies
1.2.3 SOI MOSFET Physics
1.2.4 SOI MOSFET Characterization
1.2.5 UTBB FD-SOI Process
1.3 Electrostatic Discharges (ESD)
1.3.1 Generation mechanisms and ESD stress models
1.3.2 Protection devices and protection strategies
1.3.3 ESD Characterization Methods
References
Chapter 2: BiMOS device
2.1 DC operation
2.1.1 Principle of operation
2.1.2 Fabrication process
2.1.2.1 pMOS contact
2.1.2.2 Fork-gate contact
2.1.3 Physical mechanisms
2.1.4 DC measurements
2.1.4.1 MOSFET mode of operation
2.1.4.2 Hybrid mode of operation
2.1.5 TCAD simulations
2.1.5.1 Subthreshold operation and barrier modulation
2.1.5.2 Base current
2.1.6 Low temperature measurements
2.2 ESD protection operation
2.2.1 Principle of operation
2.2.2 Isothermal high current TCAD simulations and physical mechanisms
2.2.3 Electro-thermal high current TCAD simulations and physical mechanisms
2.2.4 Carrier mobility effect on high current TCAD simulations
2.2.5 ESD measurements and DC leakage measurements
2.3 Other modes of BiMOS operation
2.3.1 Amplification element
2.4 Conclusions
References
Chapter 3: GDNMOS device
3.1 Thyristors / SCRs
3.2 Physical Mechanisms
3.3 Fabrication Process
3.4 TCAD simulations
3.4.1 Isothermal Simulations
3.4.2 Electrothermal Simulations
3.5 DC measurements
3.6 ESD measurements
3.6 Thyristor behavior through doping modification
3.7 Conclusions
References
Chapter 4: Four-gate transistor (G4-FET)
4.1 Structure and principle of operation
4.2 Model
4.3 Fabrication process
4.4 TCAD simulations
4.5 DC measurements
4.6 A fundamental application of G4-FET: Evidence of supercoupling effect
4.7 4-Gate JFET mode of BiMOS structure
4.8 Conclusions
References
Chapter 5: Band-to-Band BJT
5.1 Band-to-band tunneling effect and TFETs
5.2 Tunneling FETs on standard 28nm FD-SOI technology
5.2.1 TCAD simulations
5.2.2 TFET fabrication
5.2.3 TFET measurements
5.2.3.1 Characterization : ID(VG) for VBP=0V for P#1
5.2.3.2 Characterization : ID(VG) for VBP=±5V for P#1
5.2.3.3 Characterization : ID(VG) for different VBP values and for P#2
5.2.3.4 Characterization : ID(VD) curves for P#1
5.2.3.5 ESD behavior: TLP characterization
5.3 Tunneling FETs on standard 14nm FD-SOI technology
5.4 BET-FET devices
5.5 Band-to-band bipolar junction transistor
5.5.1 Structure and operating principle
5.5.2 TCAD Simulations
5.5.2.1 Behavior through ‘Gummel’ plots
5.5.2.2 Recombination rates and the role of STI
5.5.2.3 Base resistance (RB) modulation
5.5.2.4 Tunneling resistance (RT) modulation
5.5.2.5 Behavior through gate biasing modulation
5.5.3 B2BJT Fabrication
5.5.4 B2BJT Measurements
5.6 Conclusions
References
Chapter 6: Conclusions and perspectives
6.1 Conclusion
6.2 Future perspectives
References

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