# Synchronous clocking architectures: conclusion

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## Network of coupled PLLs

In 1995 Gill Pratt and John Nguyen proposed a distributed clock generator based on network of coupled analog PLLs . Our work is based on this architecture. For this reason, this subsection provides essential information about it.
The proposed clock generator belongs to the family of multioscillator architectures based on a network of coupled oscillators. In such a clocking scheme, Fig. 2.1, a chip is partitioned into local clock areas, each of them having its own clock generator (oscillator) which must be synchronized with its neighbors in the phase domain. The goal of the distributed PLL network is to synchronize each oscillator in phase and in frequency∗. In a steady state, such a network is a source of fully synchronous distributed local clocks.
The architecture proposed by Pratt and Nguyen is a 2 dimensional Cartesian mesh net-work, where the nodes are the local clock generators and the arcs represent the coupling links between the local generators. Each local generator is linked only with its immediate Cartesian neighbors. Such a topology requires the shortest information transmission paths – which is a main advantage of such an architecture comparing with centralized clock genera-tion approaches. The coupling between the oscillators is implemented in the phase domain via phase com-parators, Fig. 2.2(a). Each phase comparator provides a measure of the error between the phases of two oscillators. This measure is then used by the control electronics associated with each oscillator in order to provide a control signal forcing the oscillators to synchro-nize with its neighbors. The control signal impacts directly the frequency of the oscillators – which is a derivative of the oscillator phase. For each oscillator a, the phase error ea,b is defined as the difference between its own phase and the phase of its neighbor b. The phase φ and the phase error are defined modulo 2π: the most common definition of the phase error is : ea,b = (π + φa − φb)mod2π − π. (2.1).

### Blocks of the ADPLL network

In this subsection we describe the architecture and discuss the basic parameters of the ADPLL blocks in the context of clocking network. We start from the oscillator, since it is the most critical block of the ADPLL system.
The oscillator in an ADPLL generates the output clock signal with the frequency defined by the input digital M-bit digital control word. As it is explained in Section 2.2.2, the DCO is generally a DAC whose output analog quantity is the frequency of oscillations at the output. In general the DCO DAC is supposed to be linear: Fosc = F0 + ΔF K, (2.2).
where Fosc is the output frequency, ΔF is the DAC resolution (the frequency step), K is the value of the input code, F0 is the DCO initial frequency. A DCO is characterized by the following parameters:
• Frequency tuning range. It specifies the upper and lower limits of the output signal frequency. In the context of clocking network it defines the tuning range of the clock frequency.
• Central frequency. This is the middle frequency of the frequency tuning range. In this project, the central frequency of the DCO defines the nominal frequency of the generated clock.
• Frequency tuning step. This parameter is the resolution of the DCO (cf. Eq. (2.2)). It defines the overall accuracy of the system (cf. the next subsection).
• Power consumption and area. These parameters are obviously critical for the clock-ing system. They are at the base of a figure of merit allowing a comparison of different clocking approaches.
• Input word width. This is the number of bits composing the input word. Together with the frequency tuning step this parameter defines the tuning range. This parameter has a direct impact on the complexity of the error processing blocks.
• Linearity/monotonicity. The transfer function of the oscillator relates the output fre-quency with the input code. This function is usually sought to be linear (cf. Eq. (2.2). For the PLL applications, a default in the linearity is not critical, since in the steady state mode the amplitude of an input DCO code is small. However, the error on lin-earity has the same impact as the error on the DCO gain. If the error is large, the performances of the PLL can be strongly affected.
The monotonicity of the code-frequency DCO characteristic is critical for the PLL application: a local inversion of the DCO characteristic slope sign is equivalent to an inversion of the PLL feedback sign. That immediately leads to an unstable behavior. Therefore, design techniques guaranteeing the monotonicity should be employed.
• Phase noise. This parameter defines the jitter at the output of the DCO. Although the DCO jitter directly impacts the quality of the generated clock, it is much less critical than in the RF applications. This allows a use of simple and ”economic” oscillator architectures such as ring CMOS (comparing with LC resonators required in RF archi-tectures).
Since the goal of our project is a proof of feasibility of the ADPLL network based clock generation, we do not focus on a design of DCO with state-of-the art performance. The most important characteristics of the DCO for this project are those critical for functional implementation of the network: in particular the parameters related to the frequency range, frequency step and monotonicity. The specification related issues will be discussed in Sec-tion 2.2.4.

#### Specification of clocking network parameters

In this subsection we discuss the system-level specifications defining the constraints for the CMOS design of the ADPLL network. For the choice of these specifications we considered the typical parameters of the modern clocking systems. The discussed specifications are focused on the functional properties of the system such as the output frequency range and the clock error. We did not consider the constraints related to the size and with the power consumption of the blocks, seeking only a proof of the functional and physical feasibility of the architecture.

Frequency step and error processing rate

The most important specification having an impact on the system design is the clock fre-quency  tuning step of the DCO and the error processing rate (the frequency of the internal clock of the control block). These two parameters define the low limit of the output phase error (the tracking error of the regulation). The existence of a low limit of the tracking error is related to the discrete grid of the DCO output frequencies.
This phenomenon is illustrated in Fig. 2.7, on the example of a single ADPLL. Let the input reference signal is periodic, with a linear phase evolution (dotted line). The phase of the DCO output signal must approximate as close as possible this trajectory. However, the output phase can only follow the lines with discrete slopes defined by the DCO frequency grid. The slope (the frequency) can change in function of the input DCO command word arriving with cadence 1/Ts. If the input reference frequency is not exactly one of the DCO frequency grid values, an ideal control loop switches the DCO output frequency between two neighboring values (solid and dash-dot lines). There is a non-zero tracking error which can be minimized but never zeroed. It can be seen that the ”minimal” error is maximal when the reference frequency is exactly in the middle between two neighboring grid values. In this situation, the DCO frequency changes with each next input word, and the output phase error Δφmax is equal to:Δφideal = Δωπ (2.4) 2ωs.

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Multi plicity of synchronisation modes

The work of Pratt and Nguyen in  highlighted a fundamental problem specifically related to the PLL networks. A PLL network may have several modes in which the local oscillators are synchronized in frequency and in phase, but with fixed phase errors between the oscilla-tors. The residual errors may be zero or not. For the clocking applications, only the mode in which the phase errors are zero is suitable for the clocking application. However, when several synchronization modes exist, the actual mode depends on the initial conditions of the system – which cannot be controlled in practice. This section presents this phenomenon in details and provides a review of the solutions to this problem.

Modeling of the clocking network

The ADPLL network is a complex non-linear high order system. By consequence, its mod-eling is of paramount importance at all stages of design. The system-level design requires a system-level modeling where each block is represented by its behavioral macromodel. As the design of the individual blocks progresses, more detailed description of the blocks must be used (e.g., gate or transistor level). Hence, the model must be built on an open plat-form able to integrate different levels of description. In our study, the AdvanceMS tool of Mentor Graphics was used for the modeling of the system at all levels: this tool allows a si-multaneous use of VHDL, VHDL-AMS, Verilog and transistor-level Spice descriptions in a common simulation. As shown in , the VHDL description is particularly appropriate for the system-level description of the ADPLL network, outperforming Matlab Simulink-based approach in what concerns the precision and simulation time.
This section presents the methodology of behavioral modeling of a single ADPLL and of a network of ADPLLs. The presented model has been used for a validation of the theoretical studies carried out in the frame of the HODISS research project [4, 34, 35, 36, 3] and for quick virtual prototyping of the designed ADPLL network.
The studied ADPLL network is composed of three basic blocks: a phase comparator, a loop filter and a DCO. The VHDL behavioural models of these blocks are described in the three following subsections. Subsection 2.5.5 presents the simulation results of the ADPLL network.

The model of the phase comparator

The architecture of the modeled digital phase comparator is shown in Fig. 2.15. The sign de-tector determines the sign of the phase error between re f (reference clock) and div (feedback divided clock) periodic sequences of events. The events are represented by the rising edges of the signals re f and div. If re f events are leading it means that the phase error is positive, the output is ’0’. If div events are leading it means that the phase error is negative, the output is ’1’. A quantizer is used to measure the absolute phase error range and converts it into a non-signed code representing its value |eri|. The quantizer can be seen as a n-bit ADC. The arithmetic block combines the sign with the absolute value generating a 2-complement output word eri on n + 1 bits. The implemented transfer function is given in Fig. 2.6(b).

Frequency tuning in 2D array oscillator

From practical point of view, if the number of the tuning cells in stage Y is large, they should be distributed over all stages of the oscillator. Naturally, a two dimensional array DCO is obtained like in Fig. 3.9. Such a topology is used in most similar implementations [48, 45].
In this subsection we present the calculation of the output frequency for the DCO with identical tuning cells distributed over all stages. We demonstrate a possibility of a linear output frequency control.
For the analysis we made the following assumptions, which all can be ensured in practice by appropriate design of the DCO:
• number of tuning cells in all stages is the same.
• total capacitances of stages are equal and constant.
• difference in number of active tuning cells between stages does not exceed 1.
• tuning current Iti ≪ Im, so to obtain a linear frequency tuning (cf. Eq. (3.6)).

1 Introduction
1.1 Area of focus
1.1.1 Clocking in large digital circuits
1.1.2 Clock error issues
1.2 State of the art: synchronous clocking in modern SoC
1.2.1 Conventional clock trees
1.2.2 Optical distribution technique
1.2.3 Multioscillator architectures
1.2.4 Synchronous clocking architectures: conclusion
1.3 Thesis outline and contribution
2.1 Introduction
2.2 Proposed clocking architecture
2.2.1 Network of coupled PLLs
2.2.2 Digital phase synthesis
2.2.3 Blocks of the ADPLL network
2.2.4 Specification of clocking network parameters
2.3 Multiplicity of synchronisation modes
2.3.1 Definition of the problem
2.3.2 Synchronization mode selection
2.4 Stability of the PLL networks
2.5 Modeling of the clocking network
2.5.1 The model of the phase comparator
2.5.2 Loop filter
2.5.3 DCO
2.5.5 Simulation of network
2.6 Conclusion
3 Digitally controlled oscillator design
3.1 Introduction
3.2 Digital frequency tuning in ring oscillators
3.2.1 Capacitive tuning
3.2.2 Current/Voltage tuning
3.2.3 Current tuning with width modulation technique
3.2.4 Frequency tuning in 2D array oscillator
3.2.5 The choice of the coding
3.3 DCO architecture
3.3.1 Oscillator topology
3.3.2 Control algorithm
3.4 Sizing of the DCO core and tuning cells
3.5 VHDL modeling of the oscillator
3.5.1 Precise modeling of the real code-frequency characteristic
3.5.2 Synthesis of the DCO output frequency in the precise VHDL model
3.6 DCO layout desing I: the DCO floorplan
3.6.1 Cell based design
3.6.2 Power planning
3.6.3 Signal flow oriented layout
3.6.4 Guard rings
3.6.5 General DCO floorplan
3.7 DCO layout design II: cell design
3.7.1 Main inverters
3.7.2 Feedback wire and decoupling capacitors
3.7.3 Tuning inverters
3.7.4 DCO output interface
3.7.5 A, B and C bus generator
3.7.6 DCO chip
3.8 DCO chip test
3.8.1 Impact of the supply variations
3.8.2 Chip-to-chip variations
3.8.3 Power consumption
3.8.4 Linearity
3.8.5 Jitter characteristics
3.9 Conclusion
4 Digital blocks of the ADPLL
4.1 Introduction
4.2 Digital phase/frequency error measurement
4.2.1 Digital versus analog phase comparators
4.2.2 Phase comparators versus phase-frequency detectors
4.2.3 The digital PFD architecture
4.2.4 Metastability problem
4.3 Implementation of digital PFD
4.3.1 Bang-bang detector implementation
4.3.2 Time-to-digital converter
4.3.3 Implementation of PFD
4.4 Digital loop control of ADPLL network node
4.4.1 Error combining block
4.4.2 PI filter
4.4.3 Implementation
4.5 Node programming mechanism
4.6 Conclusion
5 Clock network implementation
5.1 Introduction
5.2 FPGA prototyping
5.2.1 Synthesizable DCO
5.2.2 FPGA based TDC
5.2.3 Experimental results
5.2.4 FPGA prototyping: conclusion
5.3 Silicon implementation of the clock network
5.3.1 Floorplan of the test chip
5.3.2 Design for test
5.3.3 Test chip layout
5.4 Measurement results
5.4.1 Initial frequencies of DCOs
5.4.2 Supply voltage sensivity
5.4.3 Power consumption
5.4.4 Bidirectional configuration
5.4.5 Unidirectional configuration
5.4.6 Corner to corner timing errors
5.4.7 Study of mode-locking phenomenon
5.4.8 Coefficient variation
5.5 Conclusion
6 Conclusion and Perspectives
6.1 Thesis summary and conclusions
6.2 Future work
Appendices
A VHDL models of the ADPLL blocks
B Phase error sign detection theorem proof
C Matlab scripts
D DCO test chip characterization flow
E FPGA prototyping of the clocking network
G Clocking network test chip characterization flow
Bibliography

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