TDDB modeling for antifuse bitcell design 

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Memory architecture: random access

A random access memory (RAM) usually refers to volatile memories such as SRAM and DRAM as presented in 2.1.2. However, most NVM are also organized in order to be randomly accessed i.e. any bit of data can be accessed at any time. A simple block diagram of a RAM is depicted in figure 2.6.
A random access memory is composed of peripheral circuit blocks surrounding an array. This array is accessed using Word Lines (WL) and Bit Lines (BL). A memory bitcell (which can be of any type) is connected at each intersection. For example, an array of 32 WL and 32 BL contains 1024 bitcells. Hence, the memory density is 1024-bits or 1-kb.
To use the memory, the user sets inputs on a control logic block in order to select the bits to be programmed or read in the array. A WL address is decoded, thereby selecting an entire row while every other WLs are unselected. After the WL selec-tion, a single BL or column is accessed at a BL address. Since a single WL and a single BL are selected, only one bitcell is accessed in the entire array. Thus by changing the row and column addresses, any bit can be selected.

Read-Only Memory (ROM)

As its name suggests, a Read-Only Memory cannot be reprogrammed by the user. Therefore, data are defined prior to fabrication. The basic operation is illustrated in figure 2.7.
MOSFETs are organized in a memory array and are randomly accessed. The matrix is supplied by VDD through pull-up PMOS transistors. Considering W L1 set to a high level and W L2 set to a low level, BLs BL1, BL2 and BL4 are pulled down to ground while BL3 and BL5 are pulled up to V DD. Data can be read bit-by-bit by sensing one bit line at a time or word-by-word by sensing every bit lines. Finally a code is stored in the ROM by connecting a MOS transistor at the desired cross-over points of the memory array. The programming operation is performed either using a metal or implant mask. This memory technology is therefore fully compatible with a logic CMOS process or derivative thereof. Furthermore, a ROM features a very high density.

Flash Memory

Flash memories have many attractive features. They are non-volatile, electrically programmable, electrically erasable and very dense.
A flash bitcell is composed of a single device. In fact, it is a NMOS transistor featuring an additional floating gate interposed between the channel and the gate-oxide of the MOS transistor. A typical cross-sectional view of a flash bitcell is depicted in figure 2.8.

Emerging memories

Technology nodes after technology nodes, the gate-oxide thickness has been reduced in order to enhance the performance of CMOS transistors. However, this essential improvement has a rather negative impact on semiconductor memories. Indeed, the charge retention in flash memories is more and more difficult. DRAM need to be more refreshed leading to a higher power consumption. Finally the stability of SRAM is compromised by a lower supply voltage.
Memory designers are facing more and more difficulties to follow the pace of de-vice downscaling dictated by the semiconductor roadmaps. Consequently, emerging memory technologies are being actively developed in order to propose an alternative solution for Flash (NOR and NAND) or volatile memories e.g. SRAM and DRAM.
Resistive RAM (RRAM) The underlying concept of RRAM or Conductive Bridging RAM (CBRAM) is to switch a device somewhat similar to a capacitor between a high resistive state (HRS) and a low resistive state (LRS) [22,23]. A typ-ical bitcell comprises a resistance-switching device connected in series to an access transistor. A schematic and the resistance of a cycling test are shown in figure 2.12.

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Table of contents :

1 Introduction 
2 Non-volatile semiconductor memories 
2.1 Types of semiconductor memories
2.1.1 Market trends
2.1.2 Classification Stand-alone and embedded memories Memory performance Memory architecture: random access Read-Only Memory (ROM) Flash Memory Emerging memories
2.1.3 Comparison
2.2 One-Time Programmable memories
2.2.1 OTP in semiconductor markets
2.2.2 Historical background The storage matrix Laser fuse
2.2.3 eFuse memories eFuse technologies eFuse macros
2.3 Antifuse memories
2.3.1 Programming mechanism
2.3.2 Bitcell architecture Drift antifuse bitcell Cascode antifuse bitcell Dual-port cascode bitcell Multi Antifuse cascode bitell
2.3.3 Antifuse macros
2.4 eFuse versus Antifuse
2.5 Conclusion
3 Antifuse memories and gate-oxide breakdown 
3.1 Modeling approach
3.2 Gate-oxide breakdown mechanisms
3.2.1 Current transport processes in dielectrics Fowler-Nordheim tunneling current Direct tunneling current Frenkel-Poole transport
3.2.2 Statistical approach Weibull distribution Practical statistical study on antifuse bitcells Percolation model
3.2.3 Voltage acceleration of time-to-breakdown Empirical approach
3.2.4 Physics-based models Anode Hole Injection: 1/E model Thermo-Chemical: E model Hydrogen release
3.2.5 Conclusion and perspective for antifuse bitcells
3.3 Antifuse bitcells and high-K dielectrics
3.3.1 High-K dielectric breakdown
3.3.2 Perspectives
3.4 Time-to-Breakdown characterization
3.4.1 Gate-oxide breakdown event Breakdown modes Focus on soft and progressive breakdown modes .
3.4.2 Antifuse bitcell characterization methods DC voltage ramp Successive high voltage pulses Current measurements using a series resistor Transmission Line Pulse Fast current measurements using a RF bias-Tee
3.4.3 Conclusion and perspectives
3.5 Conclusion
4 TDDB modeling for antifuse bitcell design 
4.1 Methodology
4.1.1 Typical Time-to-Breakdown measurements
4.1.2 Wearout current and voltage operating point
4.2 Wearout current modeling
4.2.1 Fowler-Nordheim tunneling Analytical expression Practical example
4.2.2 Conclusion
4.3 Time-to-breakdown modeling
4.3.1 Measurements and distributions
4.3.2 Identification of the voltage-acceleration law
4.3.3 RF measurements
4.3.4 Conclusion
4.4 Optimization of the antifuse bitcell design
4.4.1 Modeling approach Antifuse bitcell equivalent circuit Expression of Vcap Model output
4.4.2 Application and verification Antifuse bitcell dimensions Identification of parameters Results Focus on the operating point
4.4.3 Method of optimization Methodology and algorithm Results
4.4.4 Conclusion
4.5 Cascode antifuse bitcell
4.5.1 Architecture and performance
4.5.2 High-K cascode antifuse bitcell Wearout current measurements Time-to-breakdown measurements Discussion
4.6 Conclusion
5 Side effect: Bulk current overshoot 
5.1 Facts
5.1.1 Antifuse devices Single drift Single capacitor Conclusion
5.2 Characterizations of the phenomenon
5.2.1 DC characterizations
5.2.2 Impact of programming conditions Programming voltage Cumulative programming Programming current Summary & conclusion
5.3 Analysis of assumptions on the root cause
5.3.1 Electron and hole transport Wearout phase Post-breakdown phase
5.3.2 Parasitic bipolar transistor Current signs and polarities P-N-P structure Current-gain simulations
5.4 Summary and conclusion
6 Post-breakdown phase and read current 
6.1 Read operation basics
6.1.1 Read current distributions
6.1.2 Breakdown path characteristic
6.1.3 Perspectives
6.2 Impact of the post-breakdown conditions
6.2.1 Post-breakdown current limiter circuit Topology and design Performance
6.2.2 Read current distributions & characteristics Read current distributions Breakdown path characteristic Cascode bitcell
6.2.3 Discussion
6.3 Conclusion
7 32-nm CMOS Advanced antifuse memory demonstrator 
7.1 Key features and operating modes
7.1.1 Functionalities Standard programming mode Advanced programming mode Read mode
7.1.2 Specifications
7.2 Programming current limiter
7.2.1 Topology and design
7.2.2 Simulations
7.2.3 Implemented solutions
7.2.4 Conclusion
7.3 Programming detection system
7.3.1 Configurable bitline multiplexer
7.3.2 Programming current sensor
7.3.3 Post-breakdown time delay
7.4 Conclusion
8 Conclusion 


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