TECHNOLOGIES FOR POWER AMPLIFIER INTEGRATION

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BACKGROUND TO THE RESEARCH

In the recent mobile telecommunication history, a number of wireless modulation schemes have found commercial use. Transmitter devices employing these schemes all demand a power amplifier (PA) for their successful operation.
shows the PA as a part of a simple telecommunication system [1]. Bulky and high-power off-the-shelf component- based PAs are being replaced by radio-frequency (RF) integrated circuit (RFIC) PAs [2], operating from low-voltage power supplies [3]. This trend is evident in a wide spectrum of analogue and digital applications, starting from short distance (cordless phones, Bluetooth, wireless local area networks (WLANs)), to medium (RF identification (RFID)) and long distance applications (cellular phones, third generation (3G) devices) [4]. The PA remains a bottleneck in the full integration of wireless transceivers, especially if integration is done in pure silicon complementary metal-oxide semiconductor (CMOS) processes. For this reason, most commercial wireless devices use an external PA to drive an antenna.
This external device is usually fabricated in technologies superior to the silicon (Si) CMOS, such as gallium-arsenide (GaAs) heterojunction bipolar transistor (HBT) technology [5]. Nevertheless, it is not always possible to separate a PA from the rest of the system, so that designers often have to be satisfied with a simple PA design in a pure CMOS process, or alternatively, a hybrid processes such as silicon-germanium (SiGe) bipolar-CMOS (BiCMOS) process [6]. In many RF modulation schemes, such as the direct sequence spread spectrum (DSSS) technique, it is necessary to design several PAs in order to ensure operation over different channels of the same band. For example, for a system based on DSSS [7], transmission is possible over a number of channels in Industrial, Scientific and Medical (ISM) band; their centre frequencies ranging from 2.4000 GHz to 2.4835 GHz.
If a correct design methodology is not employed, designing of all PAs for all channels can be quite time consuming. Basic PA is designed around one or more active devices, either metal-oxide semiconductor field-effect transistors (MOSFETs), bipolar junction transistors (BJTs) or HBTs. Several PA output stages are commonly used in telecommunications, with Class E and Class F widely used [8]. Irrespective of the output stage, and additional to the active devices, a number of passive components (inductors and capacitors) must be included. At the schematic design level this does not present a problem, because ideal capacitors and inductors can be used for the first design. However, translating of the design onto the layout level (where layout refers to actual drawing of components on a silicon wafer) becomes more intricate. Here, designing of an inductor poses a special problem, because of a great number of inductor options [9]. Even with a proper integrated inductor topology selected, the more affordable electronic design automation (EDA) software packages do not have built-in procedures for integrated inductor netlist extraction, but designers have to rely on inductors, if any, provided in High Performance Interface Tool Kits (HIT-kits). Furthermore, the built-in netlist extractors usually interpret an inductor as simply a long piece of metal or wire (which short-circuits the nodes placed at the two ends of an inductor), thus making the extracted netlists incorrect.
Although there are a few models of integrated inductors described in literature [10-12], they are often not used by designers who are either satisfied by simulations at the schematic level or replace actual inductors with ideal inductors in order to proceed with the post-layout simulations. Drawbacks of such an approach might not be apparent at low frequencies, but they become particularly important in the design of PAs at RF, due to the fact that even small differences between actual and designed values of inductance can strongly affect the centre frequency, gain or efficiency of the amplifier. Often, these mismatches can only be seen after the fabrication of the chip is completed, thus introducing additional unnecessary chip fabrication iterations.

TABLE OF CONTENTS :

• CHAPTER 1 INTRODUCTION
  • 1.1 BACKGROUND TO THE RESEARCH
  • 1.2 RESEARCH PROBLEM AND HYPOTHESIS
  • 1.3 JUSTIFICATION FOR THE RESEARCH
  • 1.4 METHODOLOGY
  • 1.5 DEFINITIONS
  • 1.6 DELIMITATIONS OF SCOPE AND KEY ASSUMPTIONS
  • 1.7 CONTRIBUTION OF THE RESEARCH
  • 1.8 PUBLICATIONS LEADING FROM THIS RESEARCH
  • 1.9 OUTLINE OF THIS THESIS
  • 1.10 CONCLUSION
• CHAPTER 2 LITERATURE REVIEW
  • 2.1 INTRODUCTION
  • 2.2 POWER AMPLIFICATION
    • 2.2.1 Power capability
    • 2.2.2 Power consumption
    • 2.2.3 Power efficiency
    • 2.2.4 Matching for desired power
    • 2.2.5 Classification of PAs
    • 2.2.6 Techniques for performance improvement of PAs
    • 2.2.7 Temperature aspects of PAs
    • 2.2.8 Biasing
  • 2.3 INDUCTORS FOR POWER AMPLIFIER IMPLEMENTATIONS
    • 2.3.1 Inductor implementation options
    • 2.3.2 Spiral inductors on silicon and SiGe
  • 2.4 TECHNOLOGIES FOR POWER AMPLIFIER INTEGRATION
  • 2.5 RAPID POWER AMPLIFIER DESIGN AND AUTOMATION
  • 2.5.1 The need for rapid PA design
  • 2.5.2 Automating the rapid PA design
  • 2.6 CONCLUSION
• CHAPTER 3 METHODOLOGY
  • 3.1 INTRODUCTION
  • 3.2 RESEARCH METHODOLOGY OUTLINE
  • 3.3 THE IC PROCESS
  • 3.4 CONCEPTUAL DESIGN AND ALGORITHM DEVELOPMENT
  • 3.5 MODELLING, SIMULATION, AND LAYOUT DESIGN
    • 3.5.1 Modelling and simulation
    • 3.5.2 Layout design and verification
    • 3.5.3 EM simulation
    • 3.5.4 SPICE model of the HBT
  • 3.6 MEASUREMENT SETUP AND EQUIPMENT
  • 3.7 CONCLUSION
• CHAPTER 4 SYSTEM LEVEL DESIGN ROUTINE
  • 4.1 INTRODUCTION
  • 4.2 METHOD FOR DESIGNING THE CLASS-E POWER AMPLIFIERS
    • 4.2.1 Input parameters
    • 4.2.2 Subroutine outputs
    • 4.2.3 Description and flow diagram of the Class-E subroutine
  • 4.3 METHOD FOR DESIGNING THE CLASS-F POWER AMPLIFIERS
    • 4.3.1 Input parameters
    • 4.3.2 Subroutine outputs
    • 4.3.3 Description and flow diagram of the Class-F subroutine
  • 4.4 METHOD FOR OUTPUT MATCHING
  • 4.4.1 Input parameters
  • 4.4.2 Subroutine outputs
  • 4.4.3 Description of the matching network subroutine
  • 4.5 METHOD FOR DESIGNING SPIRAL INDUCTORS
  • 4.5.1 Input parameters
  • 4.5.2 Subroutine outputs
  • 4.5.3 Description and flow diagrams of inductor design subroutine
  • 4.6 MATCHING AND BIASING AT THE INPUT SIDE OF THE POWER
  • AMPLIFIER
  • 4.7 COMPLETE SYSTEM INTEGRATION
  • 4.7.1 Input parameters
  • 4.7.2 Routine outputs
  • 4.7.3 Description and flow diagram of the PA design routine
  • 4.8 CONCLUSION
• CHAPTER 5 FULL CIRCUIT DESIGN AND SIMULATION
  • 5.1 INTRODUCTION
  • 5.2 VERIFICATION OF THE SPIRAL INDUCTOR MODEL AND THE
  • INDUCTANCE SEARCH ALGORITHM
  • 5.3 VERIFICATION OF THE FULL SYSTEM INTEGRATION ROUTINE
    • 5.3.1 Lower power Class-E configuration
    • 5.3.2 Higher power Class-E configuration
    • 5.3.3 Lower power Class-F configuration
    • 5.3.4 Higher power Class-F configuration
    • 5.3.5 Choice of better Class-E and Class-F configuration
  • 5.4 FURTHER DESIGN OF THE CLASS-E AMPLIFIER
  • 5.5 FURTHER DESIGN OF THE CLASS-F AMPLIFIER
  • 5.6 CONCLUSION
• CHAPTER 6 LAYOUT, FABRICATION AND MEASUREMENT RESULTS
  • 6.1 INTRODUCTION
  • 6.1.1 Inductor measurements
  • 6.2 FULL SYSTEM INTEGRATION MEASUREMENTS
    • 6.2.1 Circuit layouts
    • 6.2.2 Packaging
    • 6.2.3 Package simulations
    • 6.2.4 The PCB design
    • 6.2.5 Measurement results
  • 6.3 CONCLUSION
• CHAPTER 7 CONCLUSIONS AND IMPLICATIONS
  • 7.1 INTRODUCTION
  • 7.2 CONCLUSIONS ABOUT THE RESEARCH PROBLEM
  • 7.3 IMPLICATIONS FOR THE THEORY
  • 7.4 IMPLICATIONS FOR FUTURE RESEARCH
  • REFERENCES
  • APPENDIX A MATLAB CODE
  • A.1 INTRODUCTION
  • A.2 MAIN PA DESIGN PROGRAM
  • A.3 CLASS-E DESIGN SUBROUTINE
  • A.4 CLASS-F DESIGN SUBROUTINE
  • A.5 IMPEDANCE MATCHING
  • A.6 INDUCTANCE VALUE OVERRIDE
  • A.7 SETUP OF INDUCTANCE SEARCH ALGORITHM PARAMETERS
  • A.8 SEARCH FOR REQUIRED INDUCTORS
  • A.9 PA NETLIST EXPORT
  • A.10 ENTERING PROCESS PARAMETERS
  • A.11 INDUCTANCE SEARCH ALGORITHM
  • A.12 EXPORT OF THE SPIRAL INDUCTOR SUBCIRCUIT
  • A.13 EXPORT OF THE PART OF NETLIST INVOLVING MATCHING
  • A.14 CALCULATING PARASITICS OF ANY DESIGNED SPIRAL INDUCTOR
• • A.15 DESIGN OF SPIRAL INDUCTORS AS A MAIN ROUTINE
  • A.16 DESIGN OF INDUCTORS WITH KNOWN GEOMETRY
  • A.17 EXPORT OF THE STAND-ALONE NETLIST OF A SPIRAL INDUCTOR
• • A.18 EXTRACTION OF INDUCTOR LAYOUT INTO A CIF FILE
  • A.19 EXTRACTION OF INDUCTOR LAYOUT INTO A GDSII FILE
  • A.20 MATCHING AS A MAIN ROUTINE
  • APPENDIX B PROCESS FILES FOR EM SIMULATIONS
  • B.1 INTRODUCTION
  • B.2 PROCESS FILE FOR 3M AMS S35 TECHNOLOGY
  • B.3 PROCESS FILE FOR TM AMS S35 TECHNOLOGY
  • APPENDIX C DESIGN METHOD – BE AT UP (PTY) LTD

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