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The MOS Electrostatics
In the middle of the channel, the MOSFET consists of a simple two-terminal device composed from a sandwich of a contact material (historically metal, but nowadays highly doped polysilicon), a thin oxide layer, and a semiconductor slab as shown in Fig. 2.6. In equilibrium, the Fermi-Levels must align since they represent the mean system potential energy. Considering a metal with the same Fermi-Level as a P-doped semiconductor, the band structure will be as illustrated Fig. 2.6.
The total structure capacitance is given by the series of the linear Cox capacitor given by « ox=tox, where « ox is the oxide material permittivity and tox the oxide thickness. The silicon capacitance Cs is dependent on the silicon surface potential s and can be obtained by solving the Poisson equation on silicon. For a P-dopped silicon with complete ionization of dopants and assuming Boltzmann statistics, the Poisson equation can be written as where (y) is the electrical potential across the semiconductor; is the electric field and F ( ) is called the Kingston function since was first proposed by Kington et al. [40], another proposition with a complete treatment using Fermi-Dirac Statistics, non-complete dopants ionization and minority carriers inclusion can be found in [41]. The surface charge Qs( s) can be calculated as Qs ( s) = »si ( s).
Carriers Transport on MOSFETs
As explained before, when a potential difference is applied between the drain and source, the mobile charges on the channel will flow due to a concentration gradient (diffusion) and the generated electric field (drift). The drift-diffusion model encapsulates this behavior as [see more details in Appendix.C ]: where Jn and Jp are the current density for electrons and holes; n and p the electrons and holes mobility; and the electric field on the x direction. The mobility parameter characterizes how fast a carrier can move when pulled by an electric field. When passing through the channel, carriers will be deflected by the lattice, in bulk Silicon, there are 3 major scattering mechanisms: Coulomb Scattering, Phonon Scattering and Surface Roughtnes Scattering.
At low temperatures and low electric fields, carriers will be scattered by the coulombic potential of the lattice. When temperature is higher, the lattice vibrations increase and phonon (mechanical vibrations quanta) scattering becomes more frequent. At higher electric fields, another scattering takes place, in this condition most carriers will be present at the rough silicon-oxide interface, and surface roughness scattering will be more present. Besides at high enough electric fields scattering events will become much more frequent and an increased electric field mobility will not increase carriers velocity and the mobility will be saturated. To model those effects, Caughey and Thomas [42] proposed a local doping antemperature low-field mobility tuned from 77K to 450K .
The Effective Silicon Mobility
For MOSFET simulations some specific mobility models were developed, where the mobility is only carried for the inversion layer and Matthiesen’s rule approximation is usually taken [43] [44]. For an more accurate mobility modelling Monte-Carlo or quantum transport simulations must be carried out [45] [46].
Usual effective mobility temperature dependency modelling considers an exponential temperature dependency. This model is valid under the assumption that one of Si’s significant scattering events is predominant. The primary approach to combine different scattering effects is Matthiessen’s rule: 1 eff = X i 1i .
Small Channel Effects in Analog Design
In the previous sections, a transistor model was developed base on some assumptions e.g the electric field on the longitudinal (Drain to Source) is small, that the channel is sufficiently long such as « edge » effects could be neglected and so an one-dimensional analysis could be done.
In real devices, specially more recent technological nodes, those assumptions break down and some important effects appear that had not been previously described. Some of effects have a deep impact on the analog design and must be considered in a temperature-aware framework. Following subsections will consider this effects an comment on their temperature drift effects.
Table of contents :
1 The need of Temperature-Aware Circuits
1.1 Circuits Reliability in Harsh Environments
1.2 Context of Temperature Considerations in Circuits
1.3 Contributions
1.3.1 Journal Papers
1.3.2 International Conferences
1.3.3 National Colloquium
1.3.4 Open Source Journals and Libraries
2 Transistor Temperature Effects
2.1 Semiconductor Temperature Effects
2.1.1 Band Gap Temperature dependency
2.1.2 Carriers Concentration
2.1.3 The Fermi Level
2.1.4 Doping
2.2 MOSFET
2.3 The MOS Electrostatics
2.3.1 Carriers Transport on MOSFETs
2.3.2 MOSFET Models
2.3.3 The Effective Silicon Mobility
2.3.4 The Charge Sheet Approximation
Regional Approximations of the Charge Sheet Model
2.3.5 Vth Temperature effects
VFB Temperature Variation
B Temperature Dependency
2.3.6 Current ZTC Point
2.3.7 Small Channel Effects in Analog Design
Velocity Saturation
Channel Length Modulation (CLM)
Drain Induced Barrier Lowering (DIBL)
2.4 Transistor Compact Models
2.4.1 Symmetric Linearization Models
Temperature Effects
2.4.2 Inversion Charge Linearization Based Models
Solutions to Charge Linearization Models
2.4.3 The UICM model
2.4.4 The BSIM 6 Model
2.5 The gm=ID methodology gm=ID Temperature Modeling on Compact Models
2.5.1 Pao-Sah and Brews gm=ID description
3 A Temperature-Aware design Methodology
3.1 Zero Temperature Coefficients (ZTC) Point
3.1.1 The gm ZTC Bias
3.2 Temperature analysis of gm=ID Parameters
3.2.1 Gate Transconductance Ratio
3.2.2 Parasitic Source/Drain Diodes
3.2.3 Self Gain
Drain Induced Barrier Lowering
Velocity Saturation
Channel Length Modulation
The gm=gds Model
Temperature Analysis
3.3 Temperature Analysis of MOSFET Capacitances
3.3.1 Varicap Temperature Analysis
Depletion and Inversion Analysis
Accumulation Mode Analysis
3.3.2 Cgs Temperature analysis
3.4 Conclusion
4 A Temperature-Aware Methodology Applications: A Study Case
4.1 Bandgap Voltage Reference
4.1.1 Temperature Analysis
4.1.2 Results
4.1.3 Conclusions
4.2 Differential Amplifier
4.2.1 Voltage Gain Temperature Analysis
4.2.2 Amplifier Gain-Bandwidth Product
4.2.3 Comparison to Strong Inversion Solution
4.2.4 Results
4.2.5 Temperature Sensitivity in Closed-Loop Operation
4.2.6 Conclusion
4.3 Active Inductance VCO
4.3.1 Active Inductance Temperature Analysis
4.4 Results
4.4.1 Conclusion
4.5 Conclusion
5 Conclusion and Perspectives
5.1 Work Conclusions
5.2 Research Perspectives
5.2.1 Multi-Objective Optimization
5.2.2 System Level Optimization
5.2.3 Technology Shrink
6 Résumé Étendu en Français
6.1 Contexte
6.2 Proposition
6.3 Résultats
6.4 Conclusion
Appendices
A Crystal Structures Statistics
A.1 Classical Statistical Mechanics
B Fermi Distribution
B.1 Fermi Level
C Drift-Diffusion Equation
C.1 Scattering and the Relaxation Time Approximation
D Effective Mobility and Matthiessen’s Rule
D.1 Mobility with Multiple Scattering Mechanisms
