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Band-modulation device (Z2-FET)
Perfect solution to overcome 60 mV/decade subthreshold swing in a MOSFET transistor is the band-modulation device. FD-SOI technology has allowed the recent discovery of the band-modulation devices. Z2-FET offers unrivalled switching capability and has a great opportunity thanks to its full compatibility with existing technology. Figure 3.6a encloses the structure of the band-modulation device: It is essentially a P-I-N diode where the gate covers only half of the body. A positive gate voltage emulates N* virtually-doped region, and P* region is induced by a negative substrate voltage (Fig. 3.6b). It results in the formation of a virtual thyristor-like NPNP structure which remains blocked even in direct polarization of the anode (VA > 0). The gate voltages form potential barriers that prevent the injection of the holes from the anode and the electrons from the cathode. The energy bands are modulated along the channel by the applied voltages (Fig. 3.6b). When VA reaches a VON value, the barriers collapse, suddenly unblocking the device. The transition between the OFF and ON states is remarkably steep (~ 1 mV/dec). The mechanism consists of a positive feedback between the injection of holes that lowers the barrier of the electrons and vice versa [66] [67]. Unlike the classical thyristor, the working principle of band-modulation devices is not based on the impact ionization. This explains the name given to the device: Z2-FET (zero subthreshold swing and zero impact ionization) [35]. Z2-FET has already been utilized for ESD protection [55], [56] made possible by the sharp switching characteristics. A similar band-modulation device is the field-effect diode which features two top gates 37]. A restriction of the FED is the gap between the two front-gates which affects ON current and the high frequency performance of the device.
Other applications of the Z2-FET as capacitorless 1T-DRAM and sharp logic switch will be investigated in chapter 3 where the operation principles and detailed device physics are discussed in details.
T-DRAM: Capacitorless Dynamic Random Access Memory
State-of-the art: the need for new memory for Internet of Things (IoT)
The Internet of Things (IoT) technology [57] is now an ubiquitous concept for interconnection and interaction between smart objects (devices with embedded sensors, on-board data processing capability, and means of communication). Since IoT is the convergence of memory, sensor, information, communication, and actuation technologies, they will use smaller and more energy efficient embedded sensor/communication technologies, advanced data analysis, and more sophisticated actuators to collect and process information. As IoT field is growing rapidly, new memory technology suited for their design is demanded. The crucial requirement for IoT memory is low power operation because it must be kept always in ON-mode. In addition, most of IoT devices will use multichip-package (MCP) designs to incorporate the CPU, GPU, memory and flash memory in one chip. As a result, developers have to reconsider their design goals, by using memory in new and innovative ways. The vast majority of embedded memories are currently charged based (DRAM, FLASH) or flip-flop based (SRAM). The other alternative storage options (which are not yet mature from commercial perspective) can be grouped into three categories: ReRAM (resistive) or MRAM (magnetic), and body-charged memories (so called floating-body DRAMs, FB-DRAMs).
Conventional 1T+1C DRAM
Traditional Dynamic Random Access Memory (DRAM) consists of one access MOS transistor and a storage capacitor where the information is saved in form of charges. There have been lots of attempts for the scaling of the transistor and the implementation of new material/structure for capacitor in response to the aggressive scale-down. The downscaling of memory elementary cell is still going on. However, difficulties related to process integration of both capacitance and access transistor are becoming insoluble. Especially for the integration in IoT devices, embedding 1T+1C cells inside the chips is paramount challenge. For this purpose, breakthrough architectures without external storage capacitor as alternatives to conventional DRAM memories draw keen attention.
Resistive RAM (ReRAM)
Resistive Random Access Memory (ReRAM) cells work on the principle of reversible switching of certain dielectrics between a conductive and a more resistive state under suitable bias conditions (Example in Fig. 4.1). These two states can represent the logic values ‘1’ and ‘0’, respectively. Conductive Bridge RAM (CBRAM) [57] takes advantage of a reversible creation of an electrochemically induced nanoscale conductive link in a special dielectric acting as an ionic conductor (so-called memristor behavior). The process of writing ‘1’ and ‘0’ in CBRAM cells is very fast (10-100 ns) and low-power. However, CBRAM is suited only as an important contender for Flash storage, since it cannot reach yet the DRAM or SRAM requirements essentially due to endurance issues and CMOS compatibility [58]–[60]. OxRRAM is an interesting alternative because it relies on a Metal/Insulator/Metal (MIM) stack and has better compatibility with CMOS processes. In addition, Cu-based Resistive Random Access Memory (Cu-ReRAM) [61] technology shows <10 ns Set/Reset speed and 10 M cycles of program endurance with huge capacity but they are still prototypes. In general, ReRAM are foreseen only as Flash replacement.
STT-RAM has become a leading candidate for future massive implementation. The principle of operation is somehow similar to that of resistive junctions (switching back and forth between high-resistance and low-resistance states, Fig. 4.2), but instead of using a dielectric material, it is based on a Magnetic Tunneling Junction (MTJ) [62], [63]. The MTJ is stable, the memory is non-volatile and requires no refreshing. The drawback, however, is the complexity of materials needed to form the MTJ. The device is more expensive and there are scalability issue due to the multiple structure compared to ReRAM. Both ReRAMs and STT-RAMs have already demonstrated their potential in terms of energy 27 (~pJ) and speed. Despite their promising potential, there is an insurmountable blockage for both approaches: the cost for additional process steps and special materials to be acceptable in CMOS. Thus, it seems that ReRAMs and STT-RAMs are for the future storage-class memory rather than for the embedded cache memory.
Floating-Body DRAMs (FB-DRAMs)
The concept of single-transistor DRAM (1T-DRAM) came out more than 20 years ago [64] and many enthusiastic variants have since been proposed [35], [36], [65]–[85]. In general, 1T-DRAMs take advantage of the floating-body effects that were usually regarded as parasitic and detrimental. In ‘1’-state, excess majority carriers (holes) are stored in the body and increase the potential, lower the threshold voltage and yield high current. State-‘0’ features lower current achieved by removing the holes from the body.
However, 1T-DRAMs have not yet reached the market for two main reasons:
– Conventional DRAMs were pacing successfully and there was no emergency for replacement.
– None of the 1T-DRAM versions was entirely convincing. Either the writing mechanisms were too demanding in power/voltage/reliability or the device compatibility with standard FD-SOI process was limited.
Here we describe three main variants and compare their operation mechanisms.
Meta-Stable DRAM (MSDRAM)
MSDRAM is a 1T-DRAM [69] based on Meta-Stable-Dip (MSD) effect where the dynamic coupling between front and back interfaces gives rise to a hysteresis in ID-VG characteristics. The front-gate voltage VG1 is swept from ‘accumulation’ to ‘depletion’ and vice-versa, and the difference in front-surface potential is reflected, by coupling effect, in the back-channel current which is monitored. The ‘0’-state corresponds to the case where both interfaces are in depletion and the OFF-current is small. In ‘0’-state, the system is in non-equilibrium deep-depletion because there are no holes available. Thus, it requires ‘refresh’. The ‘1’-state, defined when an inversion channel is formed at the back interface, is programmed by band-to-band generation at very negative front-gate voltage. The ‘1’-state does not require ‘refresh’ since accumulation of hole guarantees the equilibrium state. By applying a low VD within the memory window (Fig. 4.3), the ‘0’ and ‘1’-state can be read. Relatively thick MSDRAMs feature wide memory window (hysteresis), high memory margin I1/I0 and seconds-long retention. The fatal issue is film thinning used in advanced FD-SOI technology [86]. Below 10 nm, the supercoupling effect denies the co-existence of electron and hole channels facing each-other. The MSD effect vanishes 28 because the electron channel is needed to read the memory state, while the hole channel serves for charge storage.
Table of contents :
Chapter 1. Electrostatic doping: The concept and related devices
1.1. Introduction
1.2. Electrostatic doping
1.3. Why electrostatic doping?
1.3.1. Semiconductor technology
1.3.2. Electrostatic doping in FD-SOI technology
1.4. Emerging material devices with electrostatic doping
1.4.1. Carbon nanotube
1.4.2. Graphene
1.4.3. Silicon (Si) nanowires
1.4.4. Two Dimensional (2D) materials
1.5. FD-SOI devices with electrostatic doping
1.5.1. Tunneling Field Effect Transistor (TFET)
1.5.2. Lateral Double-diffused Metal Oxide Silicon (LDMOS)
1.5.3. Impact ionization Metal Oxide Silicon (IMOS)
1.5.4. Gated Diode merged NMOS (GDNMOS)
1.5.5. Charge Plasma Diode
1.5.6. Bipolar Charge Plasma Transistor
1.6. Conclusion
1.7. References
Chapter 2. The Hocus-Pocus diode: Fabrication, device operation and applications
2.1. Introduction
2.2. The Hocus-Pocus (HP) diode
2.2.1 Device fabrication
2.2.2 Principle of operation
2.3. The virtual P-N diode
2.3.1. Reverse current characteristics
2.3.2. Forward current characteristics
2.3.3. TCAD Simulation
2.3.4. Asymmetric characteristics
2.3.5. Semi-virtual P-N diode
2.3.6. Esaki diode characteristics
2.4. The virtual P-I-N diode
2.4.1. Characteristics
2.5 Other metamorphosis in HP diode
2.5.1 TFET and Z2-FET
2.6. Lifetime extraction in ultrathin film
2.6.1. Lifetime extraction methods
2.6.1.1. Deep depletion technique
2.6.1.2. Photo-conductance decay technique
2.6.2. Lifetime extraction method using HP diode
2.6.2.1. Forward I-V characteristic
2.6.2.2. Recombination and diffusion current
2.6.2.3. Reverse Recovery Transient (RRT) Method
2.6.2.3.1. The virtual P-N diode
2.6.2.3.2. The virtual P-I-N diode
2.6.2.4 Double gated P-I-N diode
2.7. Conclusion
2.8. References
Chapter 3. Z2-FET: capacitorless 1T-DRAM and logic switch
3.1. Introduction
3.2. Physics in capacitorless 1T-DRAM Z2-FET operation
3.2.1. DC operation
3.2.2. Transition between DC and pulse mode
3.2.3. Transient characteristics
3.3. Experimental validation of Z2-FET memory operation
3.3.1. DC operation
3.3.2. Transient mode operation
3.3.2.1. Standard memory operation
3.3.2.2. Retention
3.3.2.3. High temperature measurement
3.4. Advanced Z2-FET memory
3.4.1. Advanced Z2-FET structure: dual ground-plane
3.4.2. Selection-transistor-free Z2-FET memory array
3.5. Z2-FET as a logic switch
3.5.1. Z2-FET with single ground-plane
3.5.2. Novel Z2-FET with dual ground-plane
3.6. Conclusion
3.7. References
Conclusion and perspectives
