MOS transistors: state of art and trends
The concept for a Field Effect Transistor (FET) was invented by Lilienfeld  in 1930. It did not immediately catch the attention of the research community and the idea was not applied until 1948, when the first device was fabricated at Bell Labs . After the fabrication of the first integrated circuit (IC) in the 1958 , the topic became hot and a lot of industrial companies and researches focused their attention on transistors.
Nowadays, MOS transistors are the base of all the integrated circuits which constitute the electronic devices largely present in our life: computers, cars, phones, etc., leading to huge market place that changed our social behavior .
Metal-oxide-semiconductor field effect transistor
The microelectronics world is based on simple devices that can operate together to compute complex functions. In general, these devices are classified according to their operation principle. We focus here on the metal-oxide-semiconductor field effect transistor (MOSFET), the primary device for circuits.
Figure I-1a shows the structure. It is easier to analyze it along the vertical (x) and horizontal (y) axis separately :
o Along the x-axis we have a metal-oxide-semiconductor (MOS) structure. The semiconductor is typically nearly doped silicon (in the example, it is p-type, thus a n-MOSFET is obtained). On top of it, a silicon-dioxide layer is fabricated and serves as gate oxide. A conductive gate is placed on the top interface of the SiO2. The gate bias VG controls the electronic bands bending in the silicon, at the interface with the gate oxide. A conduction channel made of electrons is induced if VG > VT (threshold voltage). For low values of gate bias, no free carriers are present in the channel;
o Along the y-axis two highly doped regions (source and drain) are made by implantation of the silicon next to the conduction channel. Considering the case of p-type silicon film, the source and drain contacts are n++ type. The source is grounded, while a bias is applied on the drain side (drain bias, VD). For VG << VT, no carrier flow is possible and the transistor is off. For gate bias values higher than the threshold voltage, a large current of electrons flows between source and drain contacts (drain current, ID), making the device “on”.
Figure I-1b shows a schematic of drain current in logarithmic scale versus gate bias for standard n-type transistor. The characteristic has a clear switch behavior. Three regions related to the state of the device can be identified:
o Off-state: VG << VT and no current flow is possible. The current measured for VG = 0, labeled Ioff, governs the static power consumption. The off-state current has to be as small as possible to reduce power dissipation ;
o On-state: for VG > VT the conduction channel is completely created. The measured drain current at given VG and VD is labeled Ion;
o Subthreshold region: the channel starts to be created, but it is not yet complete. The slope of the ID in logarithmic scale versus VG (identified as subthreshold swing, Ss = 1/slope) defines the speed at which the device can switch between on-state and off-state. High transistor performances are obtained for steep slope (fast on-off transition) .
One of the main advantages of MOSFET is the possibility to co-integrate p-type and n-type devices on the same substrate, thanks to the use of implanted wells (CMOS technology) (Figure I-2). This allows the fabrication of integrated logic circuits which are small and fast.
The transistor scaling down and performance improvements are the main topics of microelectronics industry and research. The mainstream is defined by the well-known “Moore’s law” : every decade of technology evolution corresponds to an extra order of magnitude in transistor density (Figure I-3). In order to drive the microelectronics research & development, the International Technology Roadmap for Semiconductors (ITRS) presents the state-of-art and provides guidelines and targets for the following years. Today the fabricated transistors have 22-30 nm gate length. The last updated report of IRTS in 2014 predicts that the logic industry will have transistors with sub-10 nm gate length in 2017 (7 nm node) .
Figure I-3: Evolution of microprocessor transistors count (Moore’s law) .
However, physical limitations can compromise the device scaling down and limit the MOSFET performances:
o The decrease of the gate oxide thickness leads to an exponentially increase of the leakage current through the oxide (gate current, IG) with consequent loss of transistor-like behavior ;
o Decreasing the MOSFET dimensions, mobility degradation is due to limitations of fabrication process , . The mobility degradation is smaller structures drastically limits the transistor speed;
o In high quality Si-SiO2 interface, the subthreshold slope is not controlled by the transistor dimensions but is mainly a function of the temperature. Thus, at room temperature in the best case (SOI) it can be ≈ 66 mV/dec . To obtain faster on-off transitions, new device architecture are demanded;
o Short-channel effects (SCE): around source and drain contacts, depletion regions are present . When the device becomes smaller, the two depleted regions can overlap, leading to loss of electrostatic control of the gate bias. In order to fabricate faster and smaller transistors, new architectures are required such as multi-gate (MG) structures.
Several solutions were proposed to overcome the problems, such as the replacement of polyscristalline Si used as gate with metal , the use of high-κ dielectric material instead of silicon-dioxide , the replacement of the silicon channel with new materials with high performances , , etc. Table I-1 reports the challenge for near-term 2013-2020 according to ITRS predictions.
The short-channel effects that strongly affect the performances of small devices can be limited by particular transistor architectures. Two main ways were explored:
o STMicroelectronics®, Samsung® and GlobalFroundries® moved to MOSFET fabricated on silicon-on-insulator (SOI technology) (Figure I-4a). Fully-depleted (FDSOI) transistors lead to several practical advantages like the reduction of short-channel effect , , the possibility to use multiple threshold voltage ,  and the capability to achieve high performances (e.g., avoid mobility degradation) –. The transistor structure is still planar (i.e., the conduction channel is on a two- dimensional planes, as in Figure I-1a);
o Fin-shaped FET, called FinFET, is the architecture adopted by Intel®, Samsung®, TSMC and Global Foundries (Figure I-4b). In this case the gate surrounds 3 sides of the silicon film which acts as conduction channel (3D structure). This allows a better electrostatic control. However, the fabrication process is very different to the planar structure and huge economic effort was required to implement it. Note also that the FinFET fabrication is easier on SOI substrate . The use of SOI improves the electrostatic isolation of the conduction channel and decreases the leakage current . The feasibility and the interest of FinFET on SOI is documented in –.
Hence, independently of the implemented MOSFET architecture (planar or 3D), it is clear that SOI
substrates are superior for improving device performances. Thus, in this thesis we focus on SOI technology and, in the next sub-sections, after showing the schematic of SOI structure, a description of the main advantages and drawbacks arising from the use of SOI technology will be presented.
The SOI substrate is a multi-layer stack with a top silicon film, that acts as active layer for the devices, a buried oxide (BOX) used to isolate the active layer from the substrate and a low-doped p-type substrate used as mechanical support of the structure  (see Figure I-5).
Advantages of SOI technology
In MOSFET on bulk silicon (see Figure I-2) the conduction channel is confined close to the oxide interface. Most part of the thickness of the silicon substrate is not used but it is subject to parasitic effects such as current leakage, latch-up. Placing an oxide (called BOX or buried oxide) between the active layer and the substrate (see Figure I-4a), the conduction channel is isolated from the substrate, improving the transistor characteristics. This is the key point of SOI technology. Examples of benefits are:
– Reduction of parasitic capacitances; for example capacitances between source/drain contacts and the substrate are drastically reduced thanks to the presence of the BOX. Hence, devices fabricated on SOI work at higher frequencies than bulk technology ;
– Reduction of short-channel effects: the surfaces of the source and drain junctions are now defined by the silicon film thickness. Thus, the depletion regions are spatially limited by the presence of the buried oxide and consequently they are reduced compared to a MOSFET on bulk silicon. In case of FDSOI, the gate has a better electrostatic control on the channel , ;
– Improved device isolation: the buried oxide leads to better device isolation. Thus, phenomena like latch-up disappear leading to higher fabrication density ;
– Improvement of subthreshold swing: in FDSOI devices, the depletion region is confined in the top silicon film leading to smaller associated capacitance. Hence, the slope of drain current in weak inversion is improved. Values close to the theoretical 66 mV/dec can be achieved at room temperature , . This allows the use of smaller threshold voltage and operating voltage, thus reducing the power consumption , ;
– Immunity against radiations: devices fabricated on SOI substrate are less affected by external radiations. Since the active layer (top silicon film of the SOI structure) is isolated from the bulk substrate by the buried oxide, the impact of transient effects or ionization phenomena are drastically attenuated .
Issues with SOI technology
Despite the large numbers of advantages associated to SOI substrates, some drawbacks are still present:
– SOI quality: device performance improvements are obtained only in case of high quality SOI substrates. Thus, the carrier mobility in the silicon film has to be high and the density of defects low at silicon film-BOX interface;
– Production costs: SOI substrates are more expensive than bulk silicon. However, their use for mass production decreases the impact of the substrate price on the IC;
– Interface coupling: in FDSOI device, two silicon-SiO2 interfaces are present: one between the conduction channel and gate oxide, and the second one between the Si layer and the buried oxide. In case of ultra-thin silicon films, electrical coupling can be present between the two interfaces. The models to describe the characteristics have to be adapted to the FDSOI case;
– Floating-body effect: the holes present in the channel are confined by the buried oxide and cannot be evacuated, affecting the device performances. An example is the enhancing of leakage current – ;
– Self-heating effects: the buried oxide has smaller thermal conductivity than bulk silicon material. Thus, for high current flow, the generated heat remains confined in the conduction channel decreasing the device performances. The problem is negligible for dynamic operation of the device .
The SOI technology started with Silicon-on-Sapphire wafers (SOS) . SOS substrates improved the resistance of the integrated circuits against radiations. Consequently, this technology was very appealing for space and military applications. However, the high fabrication costs and insufficient crystal quality limited the market.
A step forward was the fabrication of devices on implanted oxygen layer which formed an insulating film under the transistor . This opened the way to new fabrication processes like Separation by Implantation of Oxygen (SIMOX) , Bond-and-Etch-Back SOI (BESOI)  and Epitaxial Layer Transfer Wafer (ELTRAN) . However, the interface quality was not high enough to introduce the SOI substrates in large-scale market.
The development of Smart-Cut™ process  completely changed the SOI production. Today, the use of this technology allows the highest quality of silicon-on-insulator substrate .
The main steps involved in the Smart-Cut™ fabrication process are (see Figure I-6):
o Two silicon wafers are required: a ‘donor wafer’ labeled A and a ‘handle wafer’ B;
o Thermal oxidation is performed on the wafer A, to growth SiO2, that will be the BOX of the final SOI substrate. The oxidation process allows a precise control of SiO2 quality and thickness;
o Hydrogen implantation is performed through the fabricated oxide. This induces micro-cavities that
define the future plan of fracture (dash line in Figure I-6 at step 3_oxidation);
o The donor and handle wafers are cleaned. The surfaces are made hydrophilic;
o The two wafers are put in contact and annealed, in order to increase the pressure of hydrogen molecules in the micro-cavities. This leads to H2 propagation which induces an horizontal fracture in the wafer A;
o The two wafers are thus separated. The wafer B is now an SOI substrate suitable for device fabrication, while the wafer A can be reused for another SOI fabrication process.
The Smart-Cut™ technology has several advantages which justify its industrial interest:
– Low density of defects is present at the interface between the top silicon film and BOX;
– High quality silicon films are obtained;
– Conventional implantation and annealing tools are used;
– The top silicon film and BOX thickness can be easily adjusted to the wanted values.
Figure I-6: Schematic of Smart-Cut™ process for SOI fabrication .
SOI substrates are clearly an asset for high quality devices but they must be of high quality. The huge fabrication progress achieved thanks to Smart-Cut™ leads todays to excellent quality substrates. However, as expressed by ITRS report, further developments on the SOI characterization (and monitoring) are required for two reasons :
– Support the research and drive the next improvements on the fabrication processes;
– Monitor the fabricated substrates and their quality during mass production.
Structural characterization techniques for SOI substrates can be divided into two groups, according to their capability to investigate geometrical dimensions or defects of the material. The characterization of SOI substrates is more complex than standard bulk silicon. The presence of a supplementary oxide (the BOX) with an additional Si-SiO2 interface requires adapted characterization methods and new approaches when the standard techniques fail.
Focusing on the geometrical dimensions, the key properties which require very accurate measurements are:
– BOX and silicon film thickness: a small variation of their values drastically affects the electrical performances of the fabricated devices. Thus, they are monitored with variable-angle single-wavelength reflectometry, single-wavelength ellipsometry and spectroscopic ellipsometry , ;
– Wafer flatness is mandatory to make the SOI substrate compatible with all the tools required for MOSFET fabrication (especially for lithography steps).
Structural defects are also present in the SOI substrate and they can degrade the performance of the future transistors . The most important are (see the schematic in Figure I-7):
– Dislocations and stacking faults are found as in standard bulk silicon;
– Surface roughness: it is a critical parameter because it can decrease the breakdown voltage on the fabricated device;
– Voids can be present at the BOX interface especially due to dust. Today this type of defects is very rare;
– “Pipes”: are conductive vias which can be present in the oxide or in the silicon film. They act as a parallel resistor, increase the off-current and reduce the device immunity against radiations;
– Metal or alkaline ions contaminations: they can affect the fabrication process (metal contaminations) or the electrical properties of the structure (alkaline ions contaminations). They decrease the minority carrier lifetime and the mobility;
– The level of residual oxygen or carbon in the silicon film: Ioff is increased and the breakdown voltage is decreased if these impurities are present;
– Fixed charges in the BOX: they affect the transistor threshold voltage and the leakage current;
– Interface traps density (Dit): these defects are due to the silicon-silicon dioxide interface and they can limit the electric properties of the transistor: poor subthreshold swing and low carrier mobility. All these defects have to be minimized in a high quality SOI substrate. This is possible only improving the fabrication processes and monitoring the SOI production. Some examples of characterization methods for structural aspects of SOI are: AFM (Atomic Force Microscope), TRXF (Total Reflection at X Fluorescence) and SIMS (Secondary Ion Mass Spectroscopy).
Table of contents :
Chapter I: General introduction
I.1 MOS transistors: state of art and trends
I.2 SOI substrates
I.3 Objectives and organization of the thesis
Chapter II: Pseudo-MOSFET for SOI characterization
II.1 The state-of-art in SOI electrical characterization
II.2 Principle of Ψ-MOSFET and parameter extraction methods
II.3 Impact of measurement
II.3.1 Measurement time setup
II.3.2 Quality of back contact
II.3.3 Role of the probes
II.3.4 Passivated top silicon film
II.4 Extension of Ψ-MOSFET to new materials: III-V-on-insulator
II.4.1 Material characterization before bonding
II.4.2 Ψ-MOSFET with pressure probes on III-V-on-insulator (III-V-OI)
II.4.3 Ψ-MOSFET with metal contacts on III-V-OI
II.4.4 Preliminary results of III-V transistors
II.5 Conclusions and perspectives
Chapter III: Split-CV in Ψ-MOSFET
III.1.1 Split-CV in MOSFET devices
III.1.2 Split-CV in pseudo-MOSFET configuration: state of the art
III.2 Effective surface and improved measurement setup
III.2.1 Dependency of Seff
III.2.2 Improved measurement setup
III.2.3 Robustness of the technique (probe effects)
III.3 Frequency effects
III.3.1 Model derivation
III.3.2 Model validation
III.3.3 Dit signature
III.4 Conclusions and perspectives
Chapter IV: Quasi-static capacitance in Ψ-MOSFET
IV.1 Introduction: quasi-static CV in MOS structures
IV.2 Quasi-static capacitance in pseudo-MOSFET
IV.2.1 Basics of QSCV for Ψ-MOSFET
IV.2.2 Comparison with LCR meter measurements
IV.3 Impact of measurement parameters
IV.3.1 Impact of back contact quality
IV.3.2 Impact of the probes
IV.3.3 Impact of scan direction
IV.4 Dit model
IV.4.1 Model derivation
IV.4.2 Model validation
IV.5 Dit extraction procedure
IV.6 Characterization of non-passivated samples
IV.6.1 Traps charging procedure
IV.6.2 Example of Dit extraction for non-passivated samples
IV.7 Surface potential computation
IV.8 Comparison of Dit profiles for different samples
IV.9 Conclusions and perspectives
Chapter V: Low-frequency noise in Ψ-MOSFET
V.1 Introduction to low-frequency noise
V.1.1 Noise parameters: the Power Spectral Density of a signal
V.1.2 LFN in MOSFETs
V.1.3 State of art of LFN in pseudo-MOSFET
V.2 LFN characterization in Ψ-MOSFET
V.2.1 Measurement setup
V.2.2 Reproducibility issues
V.2.3 Probe pressure impact
V.2.4 Impact of inter-probe distance and die area
V.3 LFN in inhomogeneous material
V.3.1 Physical model
V.3.2 Computation of LF-noise
V.4 Effective surface in LF-noise
V.4.1 Why an effective surface?
V.4.2 Quantification of effective surface
V.5 Probe penetration effects
V.5.1 Experimental evidences
V.5.2 Computation of induced defects by probe penetration
V.6 Conclusions and perspectives
Chapter VI: General conclusions and perspectives
Van Der Pauw experiments
Hall effect measurement
Table of Acronyms
Table of Constants
Table of Symbols