FEC (forward error correction)

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Table of contents

Introduction
1.1 Introduction to Viterbi Algorithm
1.2 Introduction to Viterbi decoder
1.3 Role of viterbi decoder in Digital communication systems
1.4 Previous research work
1.5 Problem statement
1.6 Objective
1.7 Outline
2 Theory
2.1 Communication systems
2.2 BEC (backward error correction)
2.3 FEC (forward error correction)
2.4 Convolution codes
2.5 Tree diagram of convolutional encoder
2.6 Trellis diagram of convolutional encoder
2.6.1 Maximum likelihood decoding
2.7 State transition diagram of convolutional encoder
2.8 Decoding convolutional codes
2.9 Viterbi algorithm a common digital signal processing function
2.10 Viterbi decoder
2.11 Viterbi Algorithm working
2.12 FPGAs (Field Programmable Gate Arrays)
2.13 Why FPGAs?
2.14 Important factors
2.14.1 Error detection capability
2.14.2 Error correction capability
2.14.3 Encoding complexity
2.14.4 Decoding complexity
2.15 Xilinx/modelsim (software used)
3 System design and implementation
3.1 Flow chart
3.2 Implementation
3.3 Viterbi decoder architecture
3.4 Synthesis results of viterbi decoder
3.5 Architecture of the enhanced decoder
3.6 Synthesis results for the enhanced algorithm
3.7 Previous work presented (comparison)
3.8 Major differences between both decoders
3.8.1 Viterbi decoder
3.8.2 New designed decoder
3.9 Pseudo code of new design decoder
4 Testing limitations and conclusions
4.1 Testing on different test samples
4.2 Limitations
4.3 Conclusions/results
4.4 Suggested future work
References