Coherence and Cache Coherence
In this chapter we describe our model of coherence and how cache coherence protocols achieve coherence. Cache coherence protocols are used in multicore systems to help coordinate memory operations.
In the next section we describe our model of coherence. This model is inspired by the work of D. Sorin and considers an ordering of memory accesses (reads and writes) to the same memory location to be a sequence of single writer followed by multiple reader periods. The invariants presented there will be used in the next chapter to demonstrate how our protocol, MESIF, achieves coherence.
We then discuss cache coherence protocols in general. We describe what is a shared memory multicore system (Section 2.2.1), cache states (Section 2.2.2), performance at- tributes of cache coherence protocols (Section 2.2.3), and the interconnection network used for inter cache communication (Section 2.2.4). The interconnection network is piv- otal to the design of the MESIF protocol as it was the development of high speed high bandwidth Intel QPI interconnect that originally spurred the development of MESIF.
In Section 2.2.5. We discuss the two traditional cache coherence protocols, snoopy and directory protocols. One of MESIF’s design goals is to have the latency comparable to a snoopy protocol but without the scalability issues of a snoopy protocol.
We also introduce the Token Coherence protocol in Section 2.2.6. Token Coherence is similar to MESIF but does not rely on broadcast messages to guarantee requests complete. Instead, Token Coherence wanted the freedom to not have to broadcast to all caches to save bandwidth; broadcasting on all requests, as MESIF does, can use a lot of bandwidth.
So transient requests in Token Coherence can fail to complete, requiring retry or eventual backo to a slower but guaranteed to succeed persistent request. In the average case, transient requests do complete and this results in Token Coherence’s two hop cache-to- cache latency. Conversely, MESIF guarantees all requests will complete without retry or backo.
How Token Coherence protocol handles transient requests was used as inspiration for extending MESIF to handle simultaneous read requests without the requests con icting, see Section 4.1 for details.
To understand coherence memory operations for memory locations, we rst give an example of the problem of coherence and a simple solution. We then dene our model of coherence for memory locations.
When a single core is reading and writing a single memory location stored in the core’s cache, we can see what behavior we expect out of reads and writes. Reads return the value in stored under that memory location in the cache. Figure 2.1a shows how a read by a core returns the value stored in the cache. Writes change the value stored in that memory location. Figure 2.1b shows how a write results in the value stored in the cache changing.
1.1 History of the MESIF Protocol
2 Coherence and Cache Coherence Protocols
2.2 Cache Coherence Protocols
3.2 MESIF Components
3.3 MESIF Coherence Invariants
3.4 Requests in MESIF .
3.5 No Simultaneous Requests in MESIF
3.6 Simultaneous Requests in MESIF
3.7 Realistic System Issues
4 MESIF improvements
4.1 Non-con icting Simultaneous Read Requests
4.2 Write Updating MESIF
4.3 Read Request Forwards as Shared .
4.4 Winning Non-Con icting Requests Without Home Message
5 Conclusions and Future Work
A Local Cache Controller SLICC Code
B Home Node and Shared Cache Controller SLICC Code
C Main Memory Controller SLICC Code
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MESIF Cache Coherence Protocol