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Circuit-Switched NoCs
The circuit-switching (CS) approach uses the resource reservation approach, also referred by the name connection-oriented approach. Basically, a message is not be injected into the network until the entire path between the source and destination is reserved. Thus, a communication is achieved by the following three steps: (i) checking or reserving a free path; (ii) initiate the communication, (iii) cancelation or deallocation phase to release the path Pham et al., 2010. This approach presents the advantage of being bufferless. As the links are pre-reserved, buffers are not needed at each hop to hold packets that are waiting for allocation, thus saving energy. However, CS-NoCs experience poor bandwidth utilization which are not suitable for real-time critical systems.
Packet-Switching NoCs
Packet-switched (PS) NoCs, also denoted by connection-less NoCs, are promoted for the efficient bandwidth and network resource usage compared to CS-NoCs Hesham et al., 2017. In this class, during the communication, data are divided into packets which find their way according to the NoC configuration: the flow the routing algorithm, an arbitration rule and the current traffic road. All these parameters will be detailed in Section 2.3.
Network-on-Chip elements
The Network-on-Chip architecture is very flexible and can be shaped accord-ing to the criticality level of the applications. Hereafter, we detail several NoC configurations.
Topology
The Network-on-Chip topology determines the physical layout and connec-tions between nodes (also called tiles). It affects profoundly the network cost-performance, hence its importance. Moreover, the topology determines the num-ber of hops (or routers) a message must traverse from the source to the destination core, thus it influences network latency significantly. Consequently, the number of hops affects directly the NoC energy consumption. Additionally, the topology dictates the total number of alternative paths between cores, which affects traffic workload and bandwidth utilization.
Since the first decision of NoC designers is the topology choice, it is useful to know the performance of the different topologies available. Here, we describe the several metrics that come in handy when comparing different topologies at design step. Degree refers to the number of links at each tile. Obviously, it follows the number of neighbors that a tile is physically connected to. The degree is a useful metric of the network’s cost when determining the implementation complexity. Thus, a higher degree requires more ports at routers, which involves a higher cost. Hop count defines the number of routers that traverse a message from the source to its destination core. It is considered as a useful parameter to calculate the message latency since every on-chip communication has at least one router traversal. Maximum channel load This metric is used to estimate the maximum band-width the network can support, or the maximum number of bits per second (bps) that can be injected by every tile into the network before its saturation.
Network-on-Chip elements
Path diversity determines the number of possible paths that a topology could provide between source to destination core. Obviously, path diversity within the topology gives flexibility and more load-balanced traffic capability to routing algorithms.
Table of contents :
Abstract
Acknowledgment
Introduction
I. Background, Context and Related work
1. Introduction to Real-Time Systems
1.1. Introduction
1.2. Task Model
1.2.1. Task Dependency
1.3. Real-time systems scheduling analysis
1.3.1. Scheduling algorithms classification
1.3.2. Scheduling characteristics
1.3.3. Scheduling analysis
1.4. Uniprocessor Scheduling
1.4.1. Rate Monotonic Scheduling
1.4.2. Deadline Monotonic Scheduling
1.4.3. Earliest Deadline First
1.5. Multiprocessor scheduling
1.5.1. Partitioned Scheduling
1.5.2. Global Scheduling
1.5.3. Semi-partitioned Scheduling
1.6. Introduction to parallel programming
1.6.1. Programming real-time systems
1.6.2. POSIX Thread
1.6.3. Fork-join model
1.6.4. Message-passing interface
1.7. Conclusion
2. On-chip Networks & Manycore architectures
2.1. Introduction
2.2. Network-on-Chip classes
2.2.1. Preliminaries
2.2.2. Circuit-Switched NoCs
2.2.3. Packet-Switching NoCs
2.3. Network-on-Chip elements
2.3.1. Topology
2.3.2. Routing Algorithms
2.3.3. Flow Control techniques
2.4. Network-on-Chip routers
2.4.1. Virtual Channels
2.4.2. Allocators and arbiters
2.5. Industrial Network-on-Chip
2.6. Simulation tools
2.7. Conclusion
3. Task Mapping: Related work
3.1. Introduction
3.2. Problem definition
3.3. NoC Resource allocation for GP-tasks
3.3.1. Dynamic Mapping
3.3.2. Static Mapping
3.4. Safety-critical real-time tasks allocation
3.5. Conclusion
II. Contributions
4. Comparative study: Priority Preemptive and Round-Robin Arbitration
4.1. Introduction
4.2. NoC switching and routing mechanisms
4.3. System model
4.3.1. Architecture model
4.3.2. Communication model
4.4. Real-time Communication simulator
4.4.1. Packages
4.4.2. NoC & Simulation Engines
4.5. Analysis
4.5.1. Fixed priority
4.5.2. Time division multiple access
4.6. Experiments
4.6.1. Conflicting communications generation
4.6.2. Simulation
4.7. Conclusion
5. DAG tasks allocation on NoC
5.1. Introduction
5.2. Related Work
5.3. System Model
5.3.1. Architecture Model
5.3.2. The DAG task model
5.4. Real-time allocation and schedulability
5.4.1. Task allocation
5.4.2. Communication latency
5.4.3. Deadlines and offsets assignment
5.4.4. Single core schedulability analysis
5.5. Results and discussions
5.6. Conclusion
6. Processor-Memory co-scheduling on NoC
6.1. Introduction
6.2. Related work
6.2.1. Real-time tasks allocation
6.2.2. Off-chip memory sharing
6.3. System Model
6.3.1. Network-on-Chip design
6.3.2. DRAM organization
6.3.3. AER DAG task model
6.4. MO-SA DAG Task Allocation
6.4.1. Exploring the neighbor solutions
6.5. AER tasks scheduling analysis and memory latency
6.5.1. Virtual sub-tasks and memory latency cost
6.5.2. On-chip communication latency analysis
6.5.3. Preemption-cost and AER tasks response time
6.5.4. Offsets and jitters assignment
6.6. Experimental Results
6.6.1. Task set generation
6.6.2. Bin-packing heuristics
6.6.3. Platform specifications & experiments protocol
6.6.4. Simulation results and discussions
6.7. Conclusion
Conclusion & Future Works
Personal publications
Bibliography
