FPGA Design Flow

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Chapter 2 Background

This chapter discusses relevant background material pertaining to the need for an enhanced static FPGA design flow. Special emphasis is given to work related to automatic floorplanning as it is the core of this thesis. This chapter begins with a discussion of basic FPGA concepts, specifically the design flow. It concludes with a brief survey of previous work related to automatic floorplanning.

FPGAs

FPGAs are general-purpose integrated circuits which can be configured to any digital function required by the designer. It is this configurability that sets FPGAs apart from ASICs. ASICs are custom hardware which cannot change their function after fabrication. Configurability also reduces the time overhead for re-implementation when the design is modified. A typical FPGA layout is shown in Figure 2.1. As seen in the figure, FPGAs contain a plethora of configurable logic blocks and routing interconnects which can be used together to implement the desired design.Modern FPGAs are heterogeneous, the need for which stems from the inefficiency of universal logic blocks when implementing certain functions. The main building blocks of modern FPGAs are Configurable Logic Blocks (CLBs), Block Random Access Memories (BRAMs) and Digital Signal Processing units (DSPs). Figure 2.2 shows a portion of the layout of the Virtex-4 FX100 FPGA which highlights the different resource types. Apart from the basic building blocks, FPGAs targeting specific applications have other block types as well. For example, the FPGA shown in Figure 2.2 has PowerPC processors which can be used in embedded applications.CLBs: The CLB is the basic logic unit of an FPGA and consists of LookUp Tables (LUTs) with 4 or 6 inputs, multiplexers and flip-flops. The LUT can be configured to implement a variety of logic, from shift registers to RAMs. The number of CLBs in the Virtex-4 FPGA varies from 1368 to 22272.BRAMs: BRAMs are on-chip memories which are available on all modern FPGAs. Xilinx FPGAs provide upto 10 Mbits of on-chip memory in 18 kBit blocks that can support true dual port operation. DSPs: DSPs implement multiply-accumulate and are primarily used in applications related to signal processing. Computationally intensive tasks can be performed efficiently on the Other Resources: Apart from the above mentioned resources, FPGAs also contain FIFOs, I/O blocks, clock managers and gigabit transceivers.

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FPGA Design Flow

The FPGA, as explained in the Section 2.1, consists of logic and routing which can be configured by the designer. Many existing commercial tools aid the designer in creating and implementing a design on an FPGA. The Xilinx flow, shown in Figure 2.3, is used to explain the basic methodology. The three main steps are enumerated below [1].

Design Entry

Any design flow begins with user input. In the FPGA design flow, the input is provided either through a schematic or HDL source. HDLs are the preferred means as they are easier to update and provide technology independence. Apart from HDLs, design constraints are added through timing and placement parameters. Synthesis constraints influence how certain modules and signals are implemented and how logic is inferred. Platform-independent HDL is optimized to a vendor-specific format by design synthesis. Behavioral information in the HDL is converted into a hierarchical or flattened structural netlist. The netlist obtained as output from design synthesis is often proprietary. In order to support third party synthesis tools, most vendors support the common Electronic Design Interchange Format (EDIF) [2].

1 Introduction 
1.1 Motivation
1.2 Contributions 
1.3 Organization 
2 Background 
2.1 FPGAs 
2.2 FPGA Design Flow 
2.2.1 Design Entry
2.2.2 Design Implementation
2.2.3 Design Verification
2.3 Improvements in Design Flow 
2.4 Automatic Floorplanning
2.4.1 Related Work
2.5 Need for a New Design Flow 
3 System Overview 
3.1 Xilinx PR Flow 
3.2 PATIS – A Modified PR Flow 
3.2.1 Automatic Floorplanner
3.2.2 Incremental Floorplanner
3.2.3 Bus Macro Insertion
3.3 Debug Support 
3.4 PlanAhead 
3.5 Experimental Verification — Proof of Concept
4 Automatic Floorplanning
4.1 FPGA Flooplanning Problem 
4.2 Proposed Overall Flow 
4.3 Netlist Extraction 
4.4 Slicing Tree Generation 
4.4.1 Overview of hMetis
4.4.2 hMetis Wrapper
4.5 IRL Generation 
4.5.1 Overview of IRLs
4.5.2 IRL Generation
4.6 Floorplan Generation 
5 Results 
5.1 Platform Description 
5.2 Benchmark Suite
5.3 Automatic Floorplanner Performance 
5.4 DMD Flow Performance
6 Conclusions and Future Work 
6.1 Future Work 
Bibliography 

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