ESD design window
In order to protect circuits from electrostatic discharges, there are two types of complementary strategies. The first one consists in preventing discharges to happen, thanks to the management of the fabrication environment of the circuit: grounding all the surfaces that can touch the components to be fabricated, using antistatic surfaces and coatings, controlling the humidity in the air and so on. However, this is not sufficient and some discharges still arise. The second strategy aims at deviating the discharges on the circuit so that they do not affect the components of the core, thanks to dedicated protection devices.
The role of the ESD protection is to evacuate a sufficient amount of current while limiting the voltage at the terminals of the protected region, in case of ESD event, so that this destructive current does not pass by the operating part of the IC. The ESD protection should be transparent in the normal IC operating mode; this means that at the operating voltage VDD its leakage current Ileak is as low as possible, and the ESD structure is not active. Its parasitic capacitance is low in order to maintain the integrity of rapid signals . The ideal anode current versus anode voltage curve (Figure 14) corresponds to a device that is normally OFF but able to switch abruptly, at a given trigger voltage, in ON mode. This trigger voltage is called VT1. If the curve features a snap-back, the holding voltage, VH, is the smallest voltage applied on the device while it is in ON state; and when the device is conductive, it has a resistivity of RON. Without snap-back, the I-V curve is close to a straight line with a slope 1/RON starting at VT1. IT2 and VT2 correspond to the failure current and voltage, respectively. The ESD protection should activate before the components of the integrated circuit suffer from breakdown, at the voltage VBD. Therefore, there is a design window, establishing that the ESD protection is ON (i.e. low impedance) for a certain voltage range [(VDD+10%) – (VBD-10%)] only. If VH is too close from VDD, there is a risk of Latch Up (LU); it means that once the protection device is activated, it stays ON even if the discharge energy is evacuated and the circuit is back to its normal operational mode. This is why a margin of 10% has to be taken. The design window depends on the IC to be protected. The ESD protection should be efficient and robust: it does not break before having sufficiently protected the IC. This means that its failure current IT2 is the highest possible. In fact, IT2 should exceed the value of the peak current of the HBM discharge corresponding to the required norm (for example 1.2 A for a 2 kV HBM). The triggering should be very fast, because ESDs happen over a short time (1 – 100 ns).
The protection device should not only be compliant with the design window in quasi-static, but also with other measurement techniques. Indeed, some transient overvoltage can appear before the protection reaches its quasi-static behavior. Such an overvoltage can be a cause of failure.
Remote protection strategy
The remote ESD protection strategy (described in Figure 16) allows to save some silicon area with respect to the local strategy . It consists in placing unidirectional protections at each I/O pads. The power clamps (protections placed between VDD and Gnd nodes) and their trigger circuit (of great dimension) are placed along the I/O ring such as to limit the parasitic resistance between two clamps. When an ESD event arises between two pads, the maximum voltage during the ESD event has to be smaller than the smallest breaking voltage that exists between those two pads. For example, the protections are here to prevent a critical voltage VCRIT to be reached across the structures of the operational circuit between the I/O pad and the ground. Considering that only one path is turned ON, the discharge flows from the I/O pad toward Gnd pad with the path depicted in Figure 16, and the following inequality has to be respected: 𝑉𝑃𝑅𝑂𝑇𝐸𝐶𝑇𝐼𝑂𝑁+𝑉𝐶𝐿𝐴𝑀𝑃+𝑅𝑃𝐴𝑅𝐴𝑆𝐼𝑇𝐼𝐶⋅𝐼𝐸𝑆𝐷< 𝑉𝐶𝑅𝐼𝑇.
where VPROTECTION and VCLAMP are the trigger voltage of the unidirectional protection and the ESD clamp respectively; RPARASITIC is the resistance value of all the metal rails involved in the path, and IESD is the ESD discharge current peak value. This example shows how important it is to make sure that the distance between two clamps is not too long.
The power clamps are typically made with huge NMOS transistors, their trigger circuit being a RC circuit that is plugged to their gate; a reverse diode is plugged in parallel between VDD and Gnd to insure the bidirectionality of the protection. The unidirectional ESD protections are usually made with diodes.
Distributed protection strategy
In the distributed ESD protection strategy, the trigger circuit is decentralized from the central clamp, and small bidirectional clamps are distributed in every I/O cell (Figure 17) . A rail Trigger is connecting all the gates of the distributed NMOS protections. The remote Trigger Circuits (TC) are connected to the rails Boost, Trigger and Gnd; they have to be placed regularly along the I/O ring. Figure 18 is depicting what happens if there is an ESD surge from one I/O pad to the second. At first the ESD event has to be detected. A fraction of the current is flowing from the ESD entry pad to the rail Boost (this current is negligible compared to the current flowing through the rail VDD). This will activate the trigger circuit, which will be maintained ON while the ESD event is occurring. The activated trigger circuit opens all the bidirectional protection that are distributed all over the chip thanks to the rail Trigger. As a result, the main ESD current can see several different paths to flow until the second I/O pad through the rail VDD. It is because of this multitude of paths that those bidirectional clamps are allowed to be designed with small dimensions.
TCAD as a predictive tool of investigation
TCAD (Technology Computer Aided Design) Synopsys Sentaurus™ tool  is ideal for simulating a single device, in order to understand the phenomena involved in the device electrical behavior, or to compare a set of devices without having to wait for measurement results (the fabrication of devices can be very time consuming). First the structure has to be generated: the different regions along with their materials are defined, the doping layers are placed as well as the electrodes (where electrical and thermal conditions will be applied). Then the device is meshed: it is discretized onto a non-uniform grid of nodes. Currents, voltages and other physical parameters can then be calculated at each node of the meshing. A trade-off has to be found for the number of nodes, between convergence and accuracy.
Our devices were meshed in 3D in a process compliant way. The simulations have been beforehand calibrated thanks to a standard NMOS structure (like the one in Figure 4). Its quasi-static ID-VG curve has been adjusted with the doping levels, the gate work function and other parameters, in order to obtain the same VTH as in the measurements. The gate stack was not simulated for reducing computation time; only a SiO2 layer was created, and a gate work function was selected (such as obtaining a similar VTH in the standard NMOS transistor). The metal interconnections were not simulated. All the simulations were done with 3D TCAD.
The aim of our simulations is not to get the exact ESD parameters such as VT1 and VH, but to be able to compare the different structures together, to understand better the phenomena provoking the different behaviors, and to have a trend.
Average Current Slope and Average Voltage Slope
For the simulation of the device, TLP method would be lengthy to reproduce, and the simulation would take a too long time before having results. Therefore, another technique is used to simulate the I-V curve: the Average Current Slope (ACS) technique (Figure 21). The device is subject to a current ramp. The rise time of the ACS is 100 ns, in order to mimic a TLP test for HBM. The voltage is initialized at 0 V and then let free to change. As a result, an I-V response of the device is obtained. It is very dependent on the slope of the current, which is adjusted thanks to the rise time of the ACS and the maximum amplitude of the current. For having the best possible equivalence to the HBM TLP measurements, the amplitude of the current ramp is chosen knowing that the failure current in all our thin-film devices is situated around 0.1 A. Therefore, in our simulations the devices are subject to a current ramp that goes from 0 to 0.1 A.
The main advantage of ACS is that only one simulation is needed for obtaining an I-V curve, while TLP requires as many simulations as the number of points that are present in an I-V curve. It has been shown  that the ACS simulation with 100 ns duration could be a good first approximation before the complete TLP measurements. Because of the short duration of the ACS event, the carriers’ flow and the trigger mechanisms are conserved. As a consequence, the ACS is a valid fast method to address a full characterization in one run.
Another advantage of the ACS is that the current is progressively raised and all the points of the I-V curve are correlated, contrary to the TLP I-V curve. Therefore, some effects – such as the overvoltage in the TLP voltage waveform – are taken into account. The overvoltage is not part of the TLP I-V curve since the data points come from an average done after the stabilization of the square waveforms, which leads sometimes to an I-V TLP curve that perfectly fits to the ESD design window but a device that is still unable to stand the intended ESD stress.
Grounded Gate NMOS
Another possibility is to use the NMOS as a Grounded Gate NMOS (GGNMOS). The gate and the source are plugged together (Figure 24), so the MOS effect is blocked, and it is the NPN parasitic Lateral Bipolar Junction Transistor (LBJT) of the structure that matters . The source of the transistor corresponds to the emitter, the substrate corresponds to the base, and the drain coincides with the collector. When a positive ESD arises, hot carriers are generated in the drain/channel junction by impact ionization. The hole current goes toward the body, thus increasing the body-source potential Vbs (through the parasitic resistor RWELL of the substrate in bulk GGNMOS). Due to this potential, the source injects electrons toward the drain, thus fully activating the parasitic bipolar transistor (with a snap-back on its ID-VD characteristics). When a negative ESD arises, the gate is biased (since it is connected to the source, which undergoes the ESD surge), thus turning ON the GGNMOS. Bulk GGNMOS benefits from volumic conduction, this is why thin-film GGNMOS (surface conduction) have a lower robustness than bulk ones. However, they trigger at a lower voltage ; as a consequence, thin-film GGNMOS are mostly used as CDM protections. The grounded-gate PMOS is not used because holes have a low mobility, therefore its performances as an ESD protection are reduced with respect to the grounded-gate NMOS. Silicide is typically removed from drains and sources in order to prevent multi-triggering (zig-zag I-V curve due to “sequential” triggering of fingers in a multi-finger device) due to the multiple fingers .
Silicon Controlled Rectifier
A Silicon Controlled Rectifier (SCR)  , also called thyristor, is a P/N/P/N doped structure. It can be seen as two merged bipolar transistors NPN and PNP that are looped (Figure 26). The SCR is a unidirectional component. A bidirectional component – the triac – is obtained by connecting two SCRs in a head to tail way (Figure 27).
The IA-VA curve of the SCR is similar to the one of the GGNMOS (with a snap-back). The strength of the SCR is its low dynamic resistance RON . Indeed, when it triggers, a very high current can flow in it. The working principle of the SCR is the loop of bipolar transistors that allows them to amplify the current. When the bipolar transistor gains are verifying the condition: β𝑁𝑃𝑁⋅β𝑃𝑁𝑃≥1 then the collector current of the PNP transistor increases, which rises the base current of the NPN transistor, thus the collector current in the NPN transistor enlarges, leading to the augmentation of the base current of the PNP transistor, which closes the loop with the raise of the collector current of the PNP transistor. The gain of the transistors depends on the doping levels and on the dimensions of the structure.
If the base of the two bipolar transistors are floating, the difference of voltage between the SCR anode and cathode should be higher than the avalanche voltage of the P-N junction in order to activate the SCR. The trigger voltage of the SCR can be lowered if a high potential is applied to the basis of the NPN transistor (which is the P-doped trigger of the SCR: GP), or if a low potential is applied to the base of the PNP transistor (N-doped trigger GN). This is the goal of the trigger circuit   .
Since the current conduction is volumic in the SCR, this device is used in the bulk. However, some efforts are made to design it on top of the SOI wafer  . The Z2-FET (Zero subthreshold swing and Zero impact ionization FET)    and GDNMOS (Gated Diode NMOS) devices result from SCR integration trial in the thin-film SOI, however those devices are very different from the SCR. Other very innovative devices are emerging, like the Z3-FET (Zero gate, Zero swing slope and Zero impact ionization FET)  for example.
Comparison between GDNMOS and GDBIMOS
The GDNMOS devices have the same VT1 as the GDBIMOS devices for same value of resistor plugged to both front gates (Figure 57). Due to the multi-triggering events at high voltage, it is difficult to compare experimentally the RON of these devices. Theoretically, RON is improved in the GDBIMOS with respect to the GDNMOS, especially if the value of the resistor plugged to its front gates is high. The reason is that the voltage applied on the gates does not decrease to 0 V with time like in GDNMOS (Figure 55 and Figure 58), so this positive gate voltage helps the conduction in the channel of the NMOS part of the GDBIMOS. It is the BIMOS part of the device that maintains the “permanent” positive gate voltage, because it benefits from a positive feedback loop: when there is a current of electrons flowing through the channel of the BIMOS, impact ionization near the drain produces holes that are attracted by the P+-doped body contact. The hole current in the body contact helps the voltage to be raised on the node of the body contact and gate, through the resistor. With an increased gate voltage, the current in the channel of the BIMOS is enhanced thanks to the MOS effect. This increased current in the channel produces more holes through impact ionization, and so on. It is the parasitic capacitances that provoke the raise in gate voltage as the anode voltage is increasing, therefore turning the device ON, and it is the body contact of the BIMOS that maintains this gate voltage while the device is ON, thus improving the RON. The I-V curves from which the data are plotted in Figure 58 are shown in Figure 59. Figure 60 compares the curves from Figure 56 (simulations of GDNMOS devices) and Figure 59 (simulations of GDBIMOS devices). Unlike in Figure 57, GDBIMOS devices clearly have a lower RON than GDNMOS devices. The higher the external resistor value, the lower RON of the GDBIMOS.
It would be interesting to remove silicide from terminals – anode, drain and source – (Figure 61) to add some resistances in the device, so that fingers all trigger at the same time uniformly. Measurements will then assess if RON still looks the same in the GDNMOS and GDBIMOS devices, without multi-triggering. With N+ doping in the drain, the GDNMOS has the behavior of a gated diode in series with a NMOS device. If RON does not change between the GDNMOS and the GDBIMOS devices, it would mean that it is the diode part that conditions RON of the device (else, the BIMOS part of the device would help the GDBIMOS to have a lower RON than in the GDNMOS).
Table of contents :
Chapter 1: Introduction
I. Presentation of the technology
1. Introduction to the FD-SOI technology
2. MOSFET in the 28 nm UTBB FD-SOI technology
II. The electrostatic discharge
1. Definition of ESD and importance of ESD protections
2. ESD stress standards
a. Human Body Model
b. Machine Model
c. Charged Device Model
3. ESD design window
4. Protection strategies
a. Local protection strategy
b. Remote protection strategy
c. Distributed protection strategy
III. Context of study and tooling
a. TLP measurements
b. VF-TLP measurements
c. DC measurements
2. TCAD as a predictive tool of investigation
a. Setup of the TCAD simulations
b. Average Current Slope and Average Voltage Slope
IV. ESD Protection devices
2. Protection devices built from NMOS devices
a. MOS switch
b. Grounded Gate NMOS
c. Bipolar MOS
3. Protection devices built from the SCR
a. Silicon Controlled Rectifier
b. Zero subthreshold swing and Zero impact ionization FET
c. Gated Diode NMOS
d. Beta-Matrix architecture
Chapter 2: ESD thin film devices
I. ESD boost solution for MOSFET and BIMOS
II. GDxMOS device for high and low-voltage ESD protection
1. GDxMOS as a high voltage protection
a. ESD robustness measurements
b. Influence of the front gates on the GDNMOS
c. Comparison between GDNMOS and GDBIMOS
d. Influence of the back gate on the GDBIMOS
e. Drain connectivities
2. GDxMOS as a low-voltage protection
a. Low-doped drain GDNMOS
b. Low-doped drain GDBIMOS
3. Silicide management in the GDxMOS
a. Silicide removal
b. Partial silicide
c. Partial silicide and drain connected to the diode gate
d. Partial silicide and drain connected to the anode
e. Fragmented partial silicide
Chapter 3: BIMOS matrices
I. BIMOS dot topology
1. 1D BIMOS dot
2. Matrix of BIMOS dot
II. Comparison of different BIMOS devices
1. Devices description
2. Results and discussion
Chapter 4: 3D ESD protections in FD-SOI
I. FD-SOI silicon continuity with bulk
II. 3D BIMOS merged SCR with silicon continuity
1. BIMOS merged SCR using P-doped trigger
2. BIMOS merged SCR using N-doped trigger
III. In-situ coupled bias resistance
1. In-situ coupled bias resistance in thin silicon film
2. In-situ coupled bias resistance in hybrid bulk
Appendix 1: TCAD setup
Appendix 2: AVS behavior of the BIMOS
Appendix 3: Résumé étendu en français
Chapitre 1 : Introduction
I. Contexte et objectifs
II. Présentation du MOSFET en technologie FD-SOI
III. Les décharges électrostatiques
1. Définition des ESD et importance des protections
2. Stress ESD standards
3. La fenêtre de conception ESD
4. Les stratégies de protection
IV. Outils de caractérisation
1. Mesures DC, TLP et VF-TLP
2. Outil TCAD : les simulations ACS et AVS
V. Les composants de protection contre les ESD
1. Diode de protection
2. Protections à base de NMOS
3. Protections à base de SCR
Chapitre 2 : Protections ESD dans le film mince
I. Boost capacitif pour NMOS et BIMOS
II. Le GDxMOS, protection ESD pour haute et basse tension
1. Le GDxMOS en tant que protection haute tension
2. Le GDxMOS en tant que protection très basse tension
3. Gestion du siliciure dans le GDxMOS
Chapitre 3 : Matrices de BIMOS
I. La topologie BIMOS dot
1. BIMOS dot en 1D
2. Matrice de BIMOS dot
II. Comparaison de différents BIMOS
Chapitre 4 : Protections ESD 3D en technologie FD-SOI avec continuité de silicium
I. BIMOS fusionné avec un SCR en 3D
II. Résistance fusionnée
1. Résistance fusionnée dans le film mince
2. Résistance fusionnée dans le substrat