The states of the system are computed through a set of diﬀerential equations. The order of the diﬀerential equations is dependent upon the number of energy storage elements in the load circuit. Power electronic systems, especially multi-phase sys-tems, are typically high order systems, and hence, are more complicated to model. There exist other types of non-linearities, based on the type of the load circuit. For example, in case of electrical drive circuit, the state (armature current/magnetic flux) varies in a rotating frame of reference. The emulator needs to be able to perform complex computations.
The dynamics of a power electronic system associated with switching are inher-ently non-linear, comprising of high frequency discontinuities. The entire system can be thought of as a hybrid system. The discontinuities – associated with switch-ing – can be regarded as transitions between discrete states. Each discrete state is then associated with a diﬀerent continuous-time transfer function.
It is possible to approximate over the discontinuities; for example, the output voltage of a buck converter is a linear function of the voltage input and the duty cycle of the PWM input. However, this approximation excludes the transient response of the system, and the eﬀect of high frequency variations in input. In order to compute the dynamics of the system for high frequency discontinuities, the emulator needs to sample at a very high frequency. It must also be able to sample the input PWM signal with a very low latency.
Since, the emulator is essentially a tool employed during the verification and validation phase of development, it needs to be flexible. It should be possible to re-configure the hardware, based on any changes in the plant model. This can also during rapid-prototyping of power electronic systems.
Hardware-in-Loop simulators are traditionally implemented on software  , using real-time processor hardware, such as xPC targets. A major advantage of such approach is ease of development and faster deployment of the solution. For example, the simulator can be designed in Simulink, and then loaded directly onto a xPC target for real-time implementation.
On the other hand, software based solutions hit bottlenecks due to the speed limitations of the processors. More significantly, due to sequential implementation, the maximum sampling rate of the emulator is indirectly proportional to the order of the system model.
Initial designs of HIL simulators for power electronic systems used FPGAs sim-ply for low latency I/O interfaces . The computation units were limited to soft-ware. However, modern FPGAs, equipped with DSP blocks capable of running at very high clock frequencies, also allow complex calculations to be implemented in firmware. Additionally, by using parallelism – inherent in FPGAs – it is possible to perform these calculations at a very high sampling rates.
FPGA based design also allows a higher degree of modularity, such that sec-tions of the system can be de-coupled from each other, and execute independently without aﬀecting the other sections. For example, a high order system model can be decomposed into sub-models, with fast and slow states. Such a decomposition can improve numerical performance, as will be demostrated in lateer chapters.  presents an example of an emulator implemented solely on FPGA based platform, thus resulting in an emulator capable of very high sampling rates. The disadvantage of using a singularly FPGA based solution is lack of configuration options. Often the design is custom built for a specific type of system model. As a tool, an emulator should provide flexibility, so that a whole range of systems can be tested using a single platform.
Due to the high sampling rate, and low input latency requirements, an FPGA is the most suitable solution to perform the state calculations. An FPGA based solution also allows parallelism, which is useful for solving high order diﬀerential/diﬀerence equations.
On the other hand, a processor/DSP based solution provides more flexibility, re-reconfigurability and ability to perform complex computations. A hybrid solution, employing HW-SW co-design, with a soft-core processor, allows both requirements to be fulfilled.
The final design parameters for this thesis were chosen on the basis of above rationale and the requirements for an HIL simulator, as given in previous section.
1. Emulator and controller implemented, each, on an Avnet Lx9 Microboard, with a Xilinx Spartan 6-Lx9 FPGA
2. HW-SW co-design, with an open-source soft-core processor IP
3. Support for multi-channel PWM input signals, with switch frequencies up to 100 kHz
4. ADC emulator with support for multiple channels, and SPI slave interface
5. Real-time logging of state variables
6. Generic and modular architecture
7. Reconfigurability of firmware1 from software
This thesis will describe the design decisions involved in the development of an emulator for a generic, high frequency switched power system. It will also present results that validate the emulator against measurement data from real hardware. The project was carried out at the Control of Power Electronics research group at the Automatic Control Laboratory of ETH Zurich. Research at the group is focused on development and real-time implementation of control algorithms for drive Systems and power converters.
This chapter presents an introduction, with a background of the applications for such an emulator, as well as the design specifications that would meet the ob-jectives. Chapter 2 will discuss the modeling aspects of a generic switched power electronic system. It will also discuss the discretization of the model. Chapter 3 will present the design for the firmware architecture that forms the backbone of both the emulator and controller boards. It will also present the selected soft-core processor used for this project, as well its interfacing with the custom logic blocks in the FPGA.
Chapter 4 will describe the logic block that performs state calculations in firmware. This block is the most important contribution to this thesis. Chapter 5 will present the results of the state calculation logic, its capabilities in terms of maximum sam-pling rate and its resource utilization on diﬀerent FPGAs. It will also present the eﬀects of quantization, and the proposed method to mitigate them. Chapter 6 will present the procedure to validate the emulator against real hardware and present the results. Finally Chapter 7 will present the conclusion and recommendations for future work.
The emulator essentially implements a mathematical model of the switched elec-tronic system, computed in discrete time. Since the emulator is not limited to model a specific type of power electronic system, it is imperative that the model of the emulated system have a generic form. In order to make the computations feasible on a FPGA-based platform, the model should also fulfill some fundamental requirements:
State Space Representation
Dynamic systems can be presented as a set of first-order diﬀerential equations that describe the relation between inputs and outputs of a system, via state variables, as given in Eq 2.1. Multiple states are defined in vector form, where the order of the vectors is equal to the order of the system. The state transfer functions f(t, x, u) and output transfer function h(t, x, u), can be both linear/nonlinear; time dependent/independent.
In the context of power electronic systems, the order (number of states) of the system typically depends on the number of energy storage elements in the circuit, for example, capacitors, inductors, electromagnetic coils/solenoids. In case of drives, mechanical energy is also stored as inertia.
The advantage of using state space representation is that it can be used to describe a system of any order. It can also describe Multiple-Input Multiple-Output (MIMO) systems. The vector representation of state variables, transfer functions particularly suits hardware implementation, as will be apparent in later chapters.
x˙(t) = f(t, x(t), u(t)); x ∈ <n; u ∈ <p (2.1)
y(t) = h(t, x(t), u(t)); y ∈ <q
FPGAs are most suited for simple mathematical operations, like addition and mul-tiplications. Modern FPGAs can make use of dedicated hardware resources to perform these calculations at very high clock frequencies. It makes sense to exploit these capabilities, and avoid more complex operations. Other mathematical opera-tions – like quadratics, exponents, trigonometric operations etc. – require complex IP blocks that, often, require multiple clock cycles to execute and are not easily scalable. Therefore, it is best to restrict FPGA based model calculations to linear systems.
Linear state space systems can be represented through matrix multiplications, as given in Eq 2.2, where dim[A] = n × n; dim[B] = n × p; dim[C] = q × n; and dim[D] = q × p. Matrix multiplications are performed as a series of Multiply-Accumulate operations, which is ideally suited for FPGA implementations.
x˙(t) = Ax(t) + Bu(t);
y(t) = Cx(t) + Du(t);
Digital systems are inherently discrete. Although there exist methods to solve diﬀerential equations analytically; they are specific to certain types of systems, and involve complex mathematical operations. Therefore, the model calculations need to be performed in discrete time. State space representation in discrete time includes a set of first order diﬀerence equations (Eq 2.3).
xk+1 = Adxk + Bduk;
yk = Cxk + Duk; (2.3)
where, xk = x(kTs)
The sampling period (Ts) and the discretization method depend on a number of factors, most importantly the frequency of the systems’ eigenvectors. Essentially, a low sampling frequency for a system with high frequency dynamics, will result in loss of accuracy. This issue is very relevant for switched power electronic systems, many of which include both very high and very low frequency dynamics.
There also exist time-variable sampling rates (variable step solvers ) that are, in fact, best suited for systems with large variation in frequencies of eigenvalues, however, this thesis will be limited to fixed-step solvers.
For a given sampling rate, the discretization method of the diﬀerential equation can also aﬀect the accuracy of the model, and can even aﬀect stability of the modeled system. Discretization methods range from simple Euler and trapezoidal methods, to more complex, higher order Runge-Kutta methods. The simplest Forward Euler method for a linear first order ordinary diﬀerential equation (ODE) is given in Eq 2.4.
x˙(t) ≈ xk+1 − xk
xk+1 = adxk + aduk = (1 + aTs)xk + bTsxk (2.4)
yk = cxk + duk
It makes sense to consider what type of model is most suitable to simulate switched power electronic systems, by looking at the mathematical models for some examples of such systems.
Multi-Phase DC-DC Converter
The multi-phase DC-DC converter is a higher-order equivalent of a simple half-bridge buck/boost/buck-boost converter  . The reasoning behind the use of multiple channels of energy storage elements (inductors) is to be able to provide higher power – using a smaller filter circuit – and to reduce switching harmonics. This is achieved by ensuring that the PWM signal to each phase leg is phase-shifted with respect to the previous phase leg by a given phase shift value.
Figure 2.1 presents the circuit diagram for a 3-phase DC-DC converter, with the IGBTs controlling the switching. The input to the system are PWM switch pulses (G1, G2, G3) provided at the gates of the transistors T1, T2, T3 respectively. Note that the switch pulses to transistors T4, T5, T6 are the exact compliment of those to transistors T1, T2, T3 respectively. The state vector is composed of the current through each phase-leg and the voltage across the capacitor. Typically, the control goal is to ensure that the voltage U0 at the output is maintained constant for a varying load. Hence, RL is a variable parameter.
Table of contents :
1.1.1 System Overview
1.2 Emulator Requirements
1.3 Design Specifications
1.3.1 Existing Architectures
1.3.2 Design Parameters
1.4 Thesis Organization
2 Generic Model for Power Electronic Systems
2.1 Design Considerations
2.1.1 State Space Representation
2.1.3 Discrete Time
2.2 Example Systems
2.2.1 Multi-Phase DC-DC Converter
2.2.2 Three phase Induction Motor Drive
2.3 Linear Parameter Varying Systems
3 Firmware Architecture
3.1 Functional Overview
3.2 Digital HW Platform
3.3 Soft-Core Processor
3.3.1 IP Selection
3.3.2 SoC Configuration
3.3.3 WB Slave Interface with Custom Logic Blocks
3.4 Analog-to-Digital Converter Emulation
3.4.2 SPI Master
3.4.3 SPI Slave
4 State Calculation Logic
4.1 Matrix-Vector Multiplication
4.2 Decomposition of the System Matrices
4.3 Module Design
4.3.1 Processing Element
4.3.2 PE Integration
4.3.3 FSM Design
4.4 Fixed Point Arithmetic
5 Hardware Validation
5.1 Testing Environment
5.1.1 Multi-phase DC-DC Converter : Model
5.1.2 Hardware Setup
5.1.3 PWM Signal
5.2 Waveform Comparison
6 Implementation Results
6.1 Maximum Clock Frequency
6.3 Example System: Sampling Rate and Resource Usage
6.4 Numerical Error
7.0.1 Future Work
A Appendix: LatticeMico32 Processor Configuration
A.2 Integrating a LM32 based SoC with Xilinx tools
A.2.1 Steps for Integration with Xilinx Tools
A.2.2 Using Block RAM for Code/Data memory
A.2.3 Using Xilinx data2mem Utility to update bitfile with Software Executable
B Appendix: Data Sheet References
B.1 Slice Architecture: Xilinx DSP48A1 Slice for Spartan6 FPGA Family
B.2 SPI Interface Timing Diagram
C Appendix: HDL Code Snippets
C.1 Dual Port Block Memory with Generic Bus-Width
C.2 Generic Depth Moving Average Filter for Binary Inputs