MJSCs on Ge and GaAs wafers
InGaAsN on Ge
MJSCs based on III-V compounds have the highest efficiency in the world and their record-efficiency has almost reached the psychological barrier of 50% for concentrator photovoltaics13. The four-junction SC based on the GaInP/GaAs/GaInAsP/GaInAs system14 has the record efficiency of 46%13, but it is fabricated by bonding of two structures grown on different wafers. The triple-junction SC based on the system InGaP/GaAs/InGaAs was metamorphic grown on a GaAs wafer and then it was inverted on a Si wafer: it has 44.4% efficiency15. However, these methods strongly limit the transfer to industry due to complicated technological steps, so monolithic MJSCs grown epitaxially without any mechanical processing steps are the most interesting. Efficiency of such MJSCs is almost the same and the record is 45.7% for the four-junction SC based on the GaInP/GaAs/GaInAs/GaInAs system at a concentration of 294 suns16. According to previous studies two junctions based on GaInP (1.85 eV) and GaAs (1.42 eV) are the most common and industrially used for the SC fabrication based on III-V semiconductors17. Initially, the bottom p-n junction in the germanium wafer is used in combination with two other junctions in GaInP and GaAs to obtain triple-junction SCs. The bandgap energy of Ge is 0.67 eV17, so the long-wavelength spectrum of sun radiation can be effectively absorbed. Moreover, the lattice- mismatch between Ge and GaAs is less than 0.1%, therefore there are possibilities for high-quality GaAs layers on Ge wafers (Figure I.2).
Figure I.2 Bandgap versus lattice constant. The grey boxes indicate nitrogen-containing alloys that have been grown lattice-matched to Ge and Si18.
In addition, according to theoretical estimations the substitution of a germanium subcell with a subcell having a bandgap energy of 1 eV could increase the 3-junction SC efficiency by a few percent, and the addition such a subcell to a 3-junction grown on a Ge wafer will allow to reach 52% under concentration19,20. InGaAsNSb with small nitrogen content is the most prospective semiconductor for this goal. III-V-N alloys (GaPNAs, InGaNAs etc.) with nitrogen content less than 5% are called dilute nitrides. It has been shown that the small addition of nitrogen leads to the large bowing parameter for the bandgap in GaAsN alloys: adding only few percent of nitrogen reduces the bandgap by hundreds of meV21. Additional content of indium in InyGa1-yNxAs1-x alloys is necessary for lattice-matching with Ge and GaAs when y=3x: it allows to epitaxially grow layers of InGaAsN on these wafers, and its bandgap energy can vary in a wide interval and reach 1 eV18 (Figure I.2). Such compounds like InGaAsN have been intensively investigated since the 1990s due to high interest in the fabrication of lasers for 1.3-1.55 μm wavelength on GaAs wafers22. However significant progress in the growth technology for photovoltaic applications has been reached only a few years ago due to the improvement in epitaxial equipment and methods. 44% is the record efficiency for the 3-junction SC grown by MBE with the bottom subcell based on the active layer of InGaAsNSb at 942 suns concentration23. A group from Finland obtained a value of 37-39% at 70 suns concentration for similar construction of 3-junction SCs grown by MBE with bottom InGaAsNSb subcell24, they also reached an efficiency of 29% at AM025 for 3-junction SCs, where the bottom subcell based on InGaAsN was grown by MBE and top subcells were grown by VPE26. Despite the result achieved using growth of InGaAsN layers, MJSCs are limited by low lifetimes of charge carriers in these alloys27. It originates from an increased defect formation due to the incorporation of nitrogen into the lattice of GaAs at lower growth temperatures of InGaNAs in comparison with the growth of GaAs. It leads to the formation of centers of non-radiative recombination with high concentrations. It is known that the p-i-n junction is preferable to the p-n junction for active layers of SCs with low lifetimes of charge carriers, since the built-in electrical field reduces the recombination in the active region and improves the collection of charge carriers. Atoms of carbon and hydrogen can incorporate during the growth of III-V compounds by VPE: it leads to the unintentional background doping and the formation of various defects which have negative influence on the lifetimes in InGaNAs layers and on the efficiency of the SC28. Therefore, the equipment of MBE with RF- plasma source of nitrogen is more preferable for the growth of InGaAsN since it allows excluding the presence of C and H in the chamber. However, even MBE-grown InGaNAs layers have the concentration of the background doping up to 1×1017 cm-3 29: it leads to big changes in the band diagram for the i-layer, so the SC efficiency can significantly decrease if the charge carrier lifetime is low in active layers. The post-growth annealing is one of the ways to improve the quality of InGaNAs dilute nitrides 30–32. Also, it has been proposed to use antimony (Sb) for the prevention of large defect formation and background doping during the growth because Sb is a good surfactant33–36. The authors showed the inhibition of the defect formation during the growth and a reduction of background doping concentration in the active layers of dilute nitrides. However, Sb has a significant disadvantage: due to deposition and accumulation on the walls inside the MBE chamber, it leads to undesirable background doping of layers in top subcells. Therefore, growth of MJSCs with Sb requires equipment with two growth chambers, but it significantly complicates the application of this technology in industry. Furthermore, the growth of such quinary alloys as InGaAsNSb is a difficult task due to the complexity of simultaneous control of material flows during the process.
In this work, the novel growth method of InGaAsN alloys by MBE without addition of antimony atoms is proposed to avoid the problems described above. It consists of using nanoheterostructures of an original design based on the InAs/GaAsN superlattice, where several InAs monolayers are separated by wide GaAsN barriers37. It opens the possibility of growth of semiconductor materials with the properties of quaternary solutions of InGaNAs with separated fluxes of indium and nitrogen. Thus, thick InAs layers of few monolayers compensate the elastic stresses arising during the growth of GaAsN on the GaAs wafer due to their lattice-mismatch. The semiconductor compound grown by the described method is called a sub-monolayer digital alloy (SDA). The method was successfully applied for the growth of III-V38–40 and II-VI41,42 compounds by MBE. Thus, in present work, the first task is the study of single-junction SCs with active layers of InGaAsN grown by SDA InAs/GaAsN on GaAs wafers.
MJSC on Si wafers
GaAs on Si
The wafer represents at least 50% of the cost of the SC so MJSCs grown on GaAs and Ge wafers are very expensive for terrestrial photovoltaic applications. The cost of the silicon wafer is the cheapest one compared to other semiconductor materials. Silicon is the second most abundant element on the Earth, after oxygen. Si accounts for 27.6-29.5% of the total mass of the earth’s crust: sand is its simplest form. However, the reserves of pure silicon, suitable for nanoelectronics, are much smaller, and the technology requires high temperatures of 1100 °C. The silicon technology has been worked out much better than other ones, so about 90% of the SCs used in terrestrial applications are fabricated on monocrystalline silicon wafers with active layers of mono-, micro-crystalline and amorphous silicon. The record efficiency SC based on silicon is 26.7%6 and it almost reaches the theoretical limit for the silicon single-junction SC.
Consequently, PV requires new approaches for high-efficiency and low-cost SCs, which can combine advantages of III-V MJSCs and silicon SCs. The fabrication of MJSCs with active layers of III-V compounds on silicon wafers is a prospective field for the photovoltaic industry. It is a real challenge for scientists, because this technology can also open ways for the fabrication of cheap optoelectronic integrated circuits with LEDs, lasers, HEMTs etc.
Historically, GaAs was the most common and most used material in the optoelectronic industry therefore it was the main reason for the development of monolithic growth technologies for this material on monocrystalline silicon wafers. Also, it was theoretically shown that single-junction and multi-junction GaAs-based SCs have the highest efficiency limit in the world 14. Thus, the majority of works about growth of III-V compounds on Si is devoted to the study of the GaAs growth on silicon wafers43–59.
In 2008, Russian authors published a comprehensive and structured review of world research in this topic43. The growth of polar III-V compounds on a non-polar silicon wafer can lead to the formation of antiphase domains, but this problem could be solved by using disoriented wafers by 4°-6°44. Furthermore, the main fundamental problems of the GaAs growth on Si are the large mismatch of lattice constant (4%) and the difference in the coefficients of thermal expansion which have not been completely solved yet17. Two ideologically different groups of methods have been proposed to solve these problems.
The first approach provides attempts to grow GaAs directly on silicon wafers using different techniques: cyclic annealing45, two-step growth46,47, the use of surfactants, for example, hydrogen48. The most common method is the growth of a very thin nucleation layer at low temperature and the subsequent growth of active layers at higher temperatures. This technology allows one to obtain better structural properties of grown GaAs layers. The possible reason of this improvement is the higher mobility of the defects leading to their annihilation in the next growth steps.
A classical single-junction SC based on GaAs was grown on a silicon wafer with this two-step method. First, a buffer GaAs layer was grown by MBE at low temperature of 390 °C, then the sample was placed in a the VPE-chamber, where active GaAs layers were grown46. But the SC efficiency was only 11.17% due to the presence of a large number of defects near the edge of the bandgap in GaAs. In another work47 the special process of annealing was carried out at a temperature of 600 °C to improve the layer characteristics after the growth of the buffer layer at a temperature of 150-300 °C. Then the SC was grown, the part of silicon wafer was shaped as an array of pyramids to reduce the effect of defects on the GaAs/Si heterointerface from the rear: it allowed to increase the efficiency from 8.7% to 10.6%. Previously, double-junction monolithic SCs based on GaAs/Si were grown in Japan by MOCVD52, where the silicon homojunction acted as the bottom subcell, with an efficiency of 19.9%.
In recent years, novel methods of GaAs growth through holes in the buffer layer of dielectric materials covering silicon have emerged 53–55. It allows avoiding the large number of antiphase domains on the Si/GaAs heterointerface in the first steps of growth. Further single crystals of GaAs would coalesce after passing through the entire thickness of the dielectric without dislocations formation. A French group has developed a method for the GaAs growth through holes in a silicon oxide (SiO2) film with a thickness of 0.6 nm by the epitaxial lateral overgrowth method allowing to obtain III-V material of good quality53. Also, the improvement of structural properties of GaAs single crystals was obtained with an increase in the growth temperature from 550 to 575 °C54. SCs based on a GaAs p-i-n junction was grown in the holes of the SiO2 film (its thickness was 200 nm) but it had an efficiency of less than 1%55.
The second group of methods is based on the use of different thick buffer layers consisting of different materials (Ge, GaInP, GaAsP etc.) giving the possibility to grow a thick GaAs layer with high quality49–51. The metamorphic method consists in a smooth transition from the lattice constant of Si to GaAs or Ge. Thus, the silicon wafer is used as a template wafer for the subsequent growth of active semiconductor structures of GaAs. The buffer layer quality is not important in this method so dislocations can introduce in it. For photovoltaic application, the silicon wafer should be considered as an active layer for the bottom subcell in the ideal MJSC so the GaAs/Si interface must have high quality for a good transport of charge carriers through it. Thus, these methods are less preferable since defects and dislocations lead to significant recombination losses of charge carriers in buffer layers. Consequently, it does not permit to use silicon for high photovoltaic performance SCs.
As described above no successful approach has been found for monolithic epitaxial growth of GaAs on silicon wafers for optoelectronic applications like SCs. The mechanical bonding method was suggested to avoid direct growth of III-V compounds on the Si wafer. Two structures are grown on their different own wafers of GaAs and Si56, then they are mechanically connected, and the top GaAs wafer is removed. As a result, a double-junction SC was fabricated with an efficiency of 19.1%. In this approach, the main efforts are focused on the development of a bonding technology allowing to reduce the effect of defect levels forming at the Si/GaAs heterointerface during the bonding process57. Nowadays, an efficiency of 27% was achieved for the tandem bonding SC based on the GaInP/Si system58, and a triple-junction SC based on GaInP/GaAs/Si was grown59. However, the method of mechanical bonding is expensive and difficult to adapt to the industrial SC production.
To summarize, the monolithic epitaxial growth of GaAs on silicon is a very difficult task for modern optoelectronics due to the high lattice-mismatch between Si and GaAs. It leads to drastic degradation of the layer quality and low SC performance. Also, the bonding technology of GaAs/Si MJSC is very complex and inconvenient for low-cost mass-production. This is why novel semiconductor materials have been explored for a lattice-matched growth in top subcells of monolithic MJSCs on silicon wafers in one process without any mechanical steps.
GaP on Si
Gallium phosphide (GaP) is one of the best choices of III-V semiconductor to be grown on Si wafers. The lattice-mismatch between GaP and Si is only 0.37%17 so it opens wide perspectives for the pseudomorphic epitaxial growth of layers based on GaP. Nowadays, there is a large number of works devoted to the development of dislocation-free growth of GaP on silicon wafers60–66. However, problems occurring during the growth process are similar to the ones in the growth of GaAs on Si. Firstly, the growth of polar GaP compounds on a nonpolar Si wafer leads to the formation of antiphase domains60. Secondly, the requirement of high growth temperatures and different coefficients of temperature expansion of GaP and Si causes the formation of threading dislocations61. These reasons seriously complicate the growth process.
The methods for avoiding these problems coincide with that proposed above for the growth of GaAs on Si. First of all, the two-steps method is used with a nucleating layer grown at low temperature in a first step62–64. This growth method of the nucleation layer is called « MEE-migration enhanced epitaxy » for MBE. It consists in an alternate interaction of the gallium and the phosphorus fluxes with the wafer surface at low temperatures of 350-400 °C. In the second step, the growth of III-V materials occurs at high temperatures of 550-600 °C with continuous fluxes of atoms. According to SEM measurements much lower density of threading dislocations arises in the sample with nucleation layer of GaP64 that positively impact the lifetime of charge carriers. Secondly, annealing procedures can also improve the quality of the GaP layers grown by MBE. For example, the multistage annealing at temperatures of 380-480 °C is preferable to the annealing at a constant temperature of 400 °C because crystal properties of GaP epilayers strongly improved65. Thirdly, the pre-epitaxial treatment of the wafer surface also can be used for optimizing the growth of GaP on Si. For instance, the silicon surface reconstructs in the growth chamber at temperatures of 700-800 °C under the gas flow of arsine (AsH3) leading to better quality of GaP layers66.
Despite the difficulties of the GaP growth on Si this concept is optimal for low-cost high-efficiency SC due to good passivation of Si by GaP and the possibility of growth of top subcells based on III-V alloys lattice-matched to GaP and Si as described below. Also, the efficiency of single-junction SCs based on the GaP/Si heterojunction should be by 1.1% higher than in a standard silicon diffusion homojunction, VOC will be higher by 49 mV and can reach 0.7 V according to the theoretical estimations67. In 1980, the first SC based on a GaP/Si heterojunction was fabricated with high VOC=0.66 V, but with it has low efficiency η=1.7% due to poor fill factor68. In 2015, similar SC with optimized contacts showed VOC=0.634 V, and the efficiency reached 12.4 %69.
InGaPAsN on Si
Through the relative success in the GaP growth on Si, new perspectives have opened in last few years for the growth of unusual kinds of semiconductors for the fabrication of MJSCs based on the integration of III-V compounds on silicon wafers. These modern materials are alloys of In-Ga-P-As-N lattice-matched to GaP and Si with small nitrogen content. However, unlike the dilute nitrides of InGaAsN lattice-matched to GaAs and Ge described above, alloys of InGaPNAs are not investigated so far and their properties are poorly known (electron and hole mobility, lifetimes of charge carriers, effective density of states in the valence and conduction bands, etc.).
As known, GaP is an indirect semiconductor but the incorporation of nitrogen atoms leads to a significant change in the band structure of GaPN. The incorporation of just 0.43 % atomic fraction of nitrogen into the GaP lattice leads to the direct band transition, and the bandgap drastically decreases for increasing nitrogen content of few percent70,71. The theoretical description of the band diagram for dilute nitrides of InGaAsN and InGaPAsN will be described in detail in the next section, since it is a very important and extraordinary feature of these semiconductors. Furthermore, an addition of indium and (or) arsenic atoms allows one to vary the bandgap energy in a wide range of 1.5 to 2.1 eV while remaining lattice-matched to Si or GaP wafers18 (Figure I.2).
The theoretical efficiency limit of double-junction SCs was simulated as a function of the bandgap energy of the bottom and top subcells72. According to such simulations 1.1 eV is the most optimal value of bandgap energy for the bottom subcell, and fortunately, it nicely corresponds to the value of silicon (Eg=1.12 eV)17. Further, the bandgap energy of InGaPAsN lattice-matched to Si varies in a wide range so 1.7 eV-InGaPNAs layers could be grown with good quality in the future. Such value is optimal for the top subcell in double-junction SCs. In this case the theoretical limit of the InGaPAsN/Si system achieves a value of 37.4% under AM1.5G18. The theoretical limit for double-junction SCs of GaInP/GaAs is only 35.1% and experimental samples have almost reached its record-efficiency value of 31.6% for monolithic SCs73. Furthermore, triple-junction SCs based on the InGaPAsN(1.8eV)/InGaPAsN(1.4eV)/Si system is preferable to the GaInP/GaAs/Ge system. The potentially achievable efficiency of a triple-junction SC based on the GaPNAs/GaPNAs/Si system (bandgap energy 2.0/1.5/1.2 eV) was theoretically calculated to be 44.5% when reaching a ~1ns minority carrier lifetime in GaPNAs74. The result of simulation creates promising background for the fabrication of high-efficiency MJSCs based on the InGaPAsN/Si system, and using cheap silicon wafers allows one to consider these SCs for future industrial production.
Attempts to synthesis of alloys with mixed anions such as GaAs1-xNx and GaP1-xNx started in the 60s of the XXth century. The main problem was the low nitrogen incorporation in InGaPAsN layers for obtaining significant nitrogen content of several percent. The nitrogen content had been obtained only at the level of the dopant until the mid-90s, so the semiconductors could not be considered as classical ternary alloys. Subsequent development of VPE and MBE technologies helped growing compounds with N content of few percents75–77. In contrast to (In)GaAsN alloys InGaPAsN ones lattice-matched to GaP have not been popular in research so these compounds are weakly investigated. One of the first quaternary alloys of GaP1-x-yAsyNx was grown on GaP wafers with contents of x=2% and y=0..19%78 and the sample with multiple quantum wells with x=2% and y=12%79 by MOVPE in Japan. In this article, the absence of dislocation was experimentally shown for compounds of GaPAsN and GaPN with different compositions and lattice-mismatch to GaP less than 0.3%. From this moment, properties of (In)GaPN(As) have begun to be investigated more deeply.
Nevertheless, the growth of InGaPAsN on Si and GaP wafers is still a challenge for researchers since there are many unsolved problems similar to the growth of InGaAsN on GaAs and Ge ones. First of all, growth of dilute nitrides layers occurs in non-equilibrium conditions at low temperature required for better nitrogen incorporation. Usually, it is less than 500 °C whereas the optimal growth temperature of GaAs and GaP is close to 600 °C. Secondly, a higher nitrogen content leads to the reduction of the bandgap energy of GaPN but in the same time it leads to a deterioration of the GaPN quality. According to previous studies, the photoluminescence intensity decreases drastically with increasing nitrogen concentration in GaPN; it decreases also in the same layers of dilute nitrides grown on Si instead of GaP wafers71,80–82. Moreover, the incorporation of nitrogen in the GaP lattice leads to the appearance of elastic stresses in pseudomorphic layers and lattice-mismatch with GaP and Si wafers. All this contributes to the appearance and increase of dislocations, appearance of antiphase domains and significant concentration of point defects (being non-radiative recombination centers) during the growth. Consequently, it can negatively impact the lifetime of charge carriers, the electron and hole mobility and other electrical properties that are crucial for optoelectronic devices. Nowadays, the number of studies concerned with defects in the InGaPNAs alloys isoperiodic to GaP is very small. The method of optically detected magnetic resonance (ODMR) has been used to find and describe a number of defects of the Gai type in GaPN(As) layers83–85, but ODMR does not allow one to obtain useful information on its position in the band diagram, values of capture cross sections and concentration. These parameters are necessary for computer simulation of SC performance and defect influence on the lifetime of charge carriers in dilute nitrides. On the other hand, deep-level transient spectroscopy (DLTS) has been used to study defects in GaP:N layers (with a nitrogen concentration of (3–8)×1018 cm–3)86–indium leads to the significant growth of the PL amplitude81 and the inhibition of defect formation in dilute nitrides85,94. However, the quality of (In)GaPN(As) lattice-matched to GaP has still remained very poor so the fabrication of SCs with high efficiency is limited by low lifetimes in InGaPAsN materials.
There are only a few studies of SCs based on InGaPAsN lattice-matched to GaP or Si. In the early 2000s, a group from NREL firstly fabricated SCs with an active layer of a quaternary alloys of GaPAsN: single-junction lattice-matched to GaP wafers95 and double-junction lattice-matched to Si wafers96 by MOCVD. The best performance for single-junction SCs was shown in the sample with the undoped GaP0.83As0.14N0.03 layer 0.64 μm thick and its important parameters are an open-circuit voltage value VOC=1.12 V, a short-circuit current density JSC=5.8 mA/cm2 and a fill factor FF=60%, and the maximum of internal quantum efficiency was close to 70%. The double-junction SC had a low efficiency of 5.2% due to the bad quality of the GaPAsN. This can be caused by two reasons. The first one is a large number of threading dislocations rising during the growth on a silicon wafer (107 cm-2) because their concentration is lower during growth on GaP wafers (105 cm-2). The second one is the high nitrogen content of 4% in the quaternary alloy leading to a significant deterioration of its optical and electrical properties as described above.
Table of contents :
I.2 MJSCs on Ge and GaAs wafers
InGaAsN on Ge
I.3 MJSC on Si wafers
GaAs on Si
GaP on Si
InGaPAsN on Si
Band structure and properties of dilute nitrides
Alternative way for growth of GaP on Si
II Experiments and methods
II.1 Growth technology
Plasma-enhanced atomic-layer deposition (PE-ALD)
II.2 Post-growth processing
II.2.2.1 Dry etching
II.2.2.2 Wet etching
Post-growth processing of SC
II.3 Experimental methods
Current –voltage characteristics
Quantum efficiency and optical measurements
Deep-level transient spectroscopy
III.1 Samples preparation
III.2 Photoelectric properties
III.3 Capacitance measurements
Quasi steady-state capacitance measurements
III.4 Structural properties
III.5 Simulation of external quantum efficiency
IV.1 Single-junction grown on GaP wafers
Quantum efficiency and current-voltage measurements of single-junction solar c
Capacitance- voltage measurements
Deep-level transient spectroscopy
IV.1.5.1 GaPAsN layer of sample #2
IV.1.5.2 GaPAsN layer of sample #3
IV.1.5.3 InP/GaPN layer of sample #4
IV.2 Double-junction solar cells on Si wafers
Quantum efficiency and I-V curves
Capacitance measurements of double-junction solar cells
IV.3 Influence of post-growth thermal annealing on solar cells
V PE-ALD growth
V.1 Growth of structures
V.2 Structural properties
V.3 Electrical properties
Current-voltage characteristics of n-GaP/p-Si structures grown by PE-ALD
Capacitance characterization of GaP/n-Si structures grown by PE-ALD
V.4 Influence of PE-ALD of GaP on the silicon wafers quality
Conclusion and perspectives
Appendix A. Contact formation for single-junction SC on GaP
A.1 Indium contacts
Appendix B. Analysis of the spectral response in InGaPAsN based solar cell
Appendix C. Contact formation for multi-junction SC on Si
C.1 Indium contacts
Appendix D. List of abbreviations and symbols
Appendix E. List of publications and conferences
Résumé de thèse