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Logarithmic Analog-to-Digital Converter
Chapter introduction
Analog-to-Digital Converters (ADC) are used to digitize an analog signal. Most of the time, the ADC has a linear behavior and directly associates an output code to the analog signal applied on its input. However, if the ADC analog input signal does not correspond to the physical quantity to be digitized through a linear behavior, the generated digital code would not linearly correspond to the physical quantity.
This is actually the case when considering the power level to be measured in the proposed VSWR regulation loop. The information to be digitized being the detected power level expressed on a logarithmic scale (in [dBm]), the analog signal coming from the power detector has an exponential behavior with respect to the physical quantity to be digitized. This exponential behavior has to be compensated using a logarithmic-behavior device in order to keep a constant digitization step along the full scale of the physical quantity.
This chapter presents the innovative architecture of a Logarithmic Analog-to-Digital Converter (LADC) that has been proposed and implemented during this Ph.D. thesis. This architecture advantageously uses the intermediate signals generated by a progressive compression logarithmic amplifier, which are regularly spaced with respect to the input signal expressed on a logarithmic scale, to perform a first step of digitization. This coarse conversion being made, a second digitization step could be performed by choosing and digitizing the intermediate signal that is linear with respect to the input signal expressed on a logarithmic scale. The coarse and the fine codes resulting from those two conversion steps are merged into a single code, which is linear with respect to the analog input signal expressed on a logarithmic scale.
Needs for logarithmic ADC & existing solutions
Needs
The usual need for analog-to-digital converters (ADC) is to digitize an analog signal in order to be able to compute the information in the digital domain with a signal processor. The analog signal to be digitized is often the output of a transducer and hence represents a physical quantity (electrical, thermal…). Figure III-1 shows the synoptic of a physical quantity digitization.
However the transducer often generates an analog signal that represents the physical quantity to be measured through an exponential law. In the context of this thesis, the power detector (detailed in the previous chapter) generates a voltage variation that is proportional to the power level expressed on a linear scale. But, the regulation loop working on the power level expressed in dBm, the power detector can be seen as a transducer that generates a voltage variation with respect to the power level expressed in dBm through an exponential law.
The difficulty now is to digitize this analog signal that represents a physical quantity through an exponential law. Using a classical linear ADC, a variation of one Least Significant Bit (LSB) does actually not represent the same range of the physical quantity when being situated at the lower or at the higher end of the digital code. This is illustrated in Figure III-2. The exponential curve on the right corresponds to the conversion of the physical quantity into the analog voltage made by the transducer. The linear stairs on the left corresponds to the digitization of the analog voltage and has been reported on the exponential law on the right to represent directly the digitization of the physical quantity. On this figure is also highlighted the physical quantity that is represented by one LSB at both the lower and the higher ends of the digital code. In this example, one LSB represents about 14% of the physical quantity scale when considering the digital code “0001”, and represents only 2% when considering the digital code “1110”.
Using a linear ADC would result in a very good precision at the higher end of the transducer scale which is much better than the requested one, but it would also result in a very poor precision at the lower end of the transducer scale which, this time, is insufficient with respect to the requested precision.
State-of-the-art
LADCs have been designed since the early 1970‟s. S. Cantarano and G.V. Pallottino have hence classified in three categories the different techniques already developed or imagined in 1973 [1]. The first one uses a linear ADC, the logarithmic conversion being performed previously in the analog domain. However, the logarithmic conversion can also be performed in the digital domain after having digitized the input signal through a linear ADC. This is the second category of LADC. Finally, the ADC can directly perform the logarithmic conversion simultaneously with the analog-to-digital conversion. Those three different categories are illustrated in Figure III-4.
Focusing on the first LADC class (Figure III-4.a), the analog logarithmic converter is usually based on logarithmic amplifiers when the input and output variables are voltages or currents. This is notably the case when using an exponential behavior component in a feedback loop (see section III.1.2.v) or when using progressive compression logarithmic amplifier (see section III.1.2.vi). But some other techniques use frequencies, the duration of time intervals or some other physical variables.
A simple combination through an AND logic gate with a digital clock signal converts the resulting pulse width in a certain number of much smaller pulses with a constant width that have to be counted in order to obtain a digital quantity corresponding to the logarithm of the input voltage Vin. Although this implementation is much closer to the third class of LADC (Figure III-4.c) rather than the first one as the ADC cannot be separated from the logarithmic converter, it illustrates the principle of some alternative techniques that uses the duration of time intervals or some other physical variables.
Digital logarithmic converters
Let us now focus on the second category of LADCs that uses a logarithmic converter in the digital domain following the linear ADC (Figure III-4.b). In general, a floating point rather than a true logarithmic representation is used [1], where F denotes the current number of bits of the fraction (mantissa), E the current number of bits of the exponent. There are several different methods for the floating point representation of a number but the widely used one is the true floating point where the number N is given by the expression (III.3).
Since the logarithmic conversion is realized with digital techniques on quantized information all the problems of accuracy are now to be considered with reference to the ADC that must accept a wide input dynamic range. This is the reason why such digital solution cannot be implemented regarding our application where the covered dynamic range should be very wide. However many different implementations of floating-point converters are presented in [1] that can be of special interest for applications requesting modest dynamic range.
Logarithmic pipeline ADC
An 8-bit logarithmic pipeline ADC is proposed in [3] that pipelines 5 stages of 1.5-bit sub- ADCs, much like a linear pipeline ADC, followed by one 2-bit logarithmic flash ADC as can be seen on the architecture of Figure III-7.a. However, instead of a 3-level multiplying DAC (MDAC), one of three gain settings is selected, by switching in different values for the feedback capacitor across an operational amplifier, depending on the sub-ADC decision as shown in Figure III-7.b. The 1.5 bit-perstage architecture is built with a certain overlap between the different stages. This redundancy relaxes the requirements on comparator accuracy and reference voltage accuracy.
It has to be noticed that the logarithmic function needs a different set of reference voltages and gains on each stage (see Figure III-7.a). The major interest of [3] actually lies in the rescale of the dynamic range between the different stages. This is also one major drawback for this solution as creating many amplifiers with different gains induces a high cost in terms of complexity which reduces the flexibility of the implemented solution. Moreover the accuracy of several gain steps is often difficult to be reached.
Table of contents :
Acknowledgements
Outline
List of figures
List of tables
General introduction
CHAPTER I. CONTEXT OF THE STUDY
Chapter introduction
Chapter outline
I.1. Building a WLAN-WPAN system at 60GHz
I.1.1. Introduction and targeted applications
I.1.2. Millimeter-Wave frequencies
I.1.3. The IEEE 802.15.3c & WirelessHD standards
I.2. mmW transmitters in Silicon technology
I.2.1. Transmitter architectures
I.2.2. Power Amplifier
I.3. Antenna impedance variation with environmental conditions
I.3.1. Introduction to standing wave formation
I.3.2. 60GHz VSWR measurements
I.3.3. Effects on Power Amplifiers
I.4. Regulation of the antenna VSWR in a 60GHz power amplifier
I.4.1. System architecture
I.4.2. Integrated power detectors
I.4.3. System requirements
Chapter conclusion
Chapter references
CHAPTER II. A 60GHZ 65NM CMOS POWER DETECTOR
Chapter introduction
Chapter outline
II.1. State of the art
II.1.1. Power detector
II.1.2. Power coupler
II.2. Chosen solution and Circuit Design
II.2.1. Power detector
II.2.2. Power coupler
II.3. Circuit physical implementation for testability
II.3.1. Circuit synoptic
II.3.2. Circuit implementation
II.3.3. Full circuit physical implementation
II.4. Measurement results
II.4.1. S-parameters
II.4.2. Input power sweep
II.4.3. Load-pull measurements
Chapter conclusion
Chapter references
CHAPTER III. LOGARITHMIC ANALOG-TO-DIGITAL CONVERTER
Chapter introduction
Chapter outline
III.1. Needs for logarithmic ADC & existing solutions
III.1.1. Needs
III.1.2. State-of-the-art
III.2. Proposed innovating solution
III.2.1. Observations on a progressive compression logarithmic amplifier
III.2.2. Coarse conversion
III.2.3. Fine conversion
III.2.4. Calibration considerations
III.2.5. Advantages of this innovating solution
III.3. Circuit physical implementation
III.3.1. Implementation overview
III.3.2. Design considerations
III.3.3. Transient simulations
III.3.4. Frequency and noise limitations
Chapter conclusion
Chapter references
CHAPTER IV. VSWR REGULATION
Chapter introduction
Chapter outline
IV.1. Regulation architecture
IV.1.1. State of the art
IV.1.2. Proposed solutions
IV.2. Circuit design and implementation for testability
IV.2.1. Add-ons on already presented blocks
IV.2.2. Adjacent circuits
IV.2.3. Full circuit physical implementation
IV.3. Analog open-loop simulations
IV.3.1. Simulation configuration
IV.3.2. Power sweep simulations
IV.3.3. Load-pull simulations
IV.4. Measurement results
IV.4.1. Measurement configuration and procedure
IV.4.2. DAC measurements
IV.4.3. LADC measurements
IV.4.4. Power sweep measurements
IV.4.5. Load-pull measurements
IV.5. VSWR-regulation concept
IV.5.1. Concept overview
IV.5.2. Algorithm to be implemented in the digital decision block
IV.5.3. Table establishment in a simple practical case
Chapter conclusion
Chapter references
CHAPTER V. SYSTEM SIMULATIONS
Chapter introduction
Chapter outline
V.1. System co-simulation
V.1.1. Introduction
V.1.2. Co-simulation implementation
V.1.3. Difficulties and solutions
V.1.4. Simulation results
V.2. Transient simulation speedup
V.2.1. Theoretical speedup
V.2.2. Practical speedup
Chapter conclusion
Chapter references
