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A Zedboard development board  with a Xilinx Zynq-7000 (XC7Z020-CLG484-1) was provided as the basis for the platform. The Zedboard incorporates volatile RAM and persistent FLASH memory, buttons, switches, an OLED screen, Ethernet con-nectivity and several interfaces for peripherals. The main component of the board, the Zynq-7000, features a dual-core ARM Cortex-A9 processor coupled with a Xilinx Artix-7 FPGA along with modules and connections devoted to efficient communica-tion between the two. On the Zedboard are five Pmod connectors which are General Purpose Input/Output (GPIO) interfaces defined by Digilent Inc . The Pmod is a 2×6 pins connector.
The FPGA is used for the cross correlation part of the matching pursuit algorithm.
The dictionary learning algorithm is performed in the CPU.
In short, programming an FPGA involves writing code in a Hardware Description Language (HDL) defining a digital circuit and its structure/behavior, after which a design tool synthesizes and verifies the design, ultimately generating a bitstream with which the programmable logic is configured. The configuration is volatile, meaning the FPGA will be completely unprogrammed if the power is turned off. This is why a separate memory device is typically loaded with the bitstream and automatically programs the FPGA each time the device is turned on. Compared to a general CPU, the hardware implemented on an FPGA is task specific and optimized to execute actions in parallel, significantly increasing performance.
The ADC is a Santa Fe Analog Front End (MAXREFDES5#)  by Maxim Integrated. It has a 16 bit resolution and features inputs accepting voltages ranging from 10 V and currents between 4 mA and 20 mA. The main component in the Santa Fe Ana-log Front End is the MAX1301 chip. The ADC communicates via the SPI protocol through the Pmod interface. Firmware is available from Maxim’s product page .
When sampling analog signals, an anti-aliasing filter for cutting off high frequen-cies must be used between the vibration sensor and the ADC. The Nyquist-Shannon sampling theorem states that the sampling rate must be at least twice that of the highest frequency component of the signal being sampled. Aliasing occurs when this criterion is not satisfied. Aliasing is when data points from a much higher fre-quency signal are mistaken in the sampled signal for being of a lower frequency. The filter will be disregarded in this thesis, however.
The pump controller is a Digilent OD1  open drain output with four different outputs independently controlled by the host board through a Pmod connector. The OD1 can sustain up to 20 V and 3 A continuously which is plenty for this application.
Figure 2.1 illustrates the Zedboard with the peripherals enumerated.
FIGURE 2.1: The Zedboard-based platform in its plastic housing.
A — ZYNQ-7000, main computer chip (underneath cooling fins).
B — Maxim Santa Fe AFE, analog-to-digital converter.
C — Digilent OD1, open drain output.
Protocols and development tools
The Maxim Santa Fe ADC uses the Serial Peripheral Interface (SPI) to communicate with other devices and the Zedboard supports many communication protocols in-cluding SPI.
SPI is a synchronous serial communication bus commonly used for microcontroller and peripheral communication. Two nodes communicate at a time, one being the master that initiates the communication and the other being the slave. It is full du-plex, meaning both nodes send and receive data simultaneously. It generally consists of four signals.
To program the components of the Zedboard multiple software applications are needed. In the case of this report, the development process can be divided into three different stages and applications used.
Xilinx Vivado  is used to configure the programmable logic, allowing for analysis and synthesis of HDL-designs.
This is the second step of the development process (the first being physically inter-connecting the devices), where peripherals, processing units and other HDL mod-ules are created and coupled together in the programmable logic. Aspects of the ARM Cortex A9 CPU in the Zynq chip as well as its built-in modules are configured, along with connections to ports on the Zedboard itself. Programming of the FPGA is done using Vivado, it comes with many board presets which allows it to commu-nicate with the Zedboard without much user intervention. A 1-year Vivado license came with the purchase of the Zedboard but there are free versions available too.
Vivado High-Level Synthesis  allows for the creation of HDL modules targeted at Xilinx devices to be used in Vivado without having to explicitly develop them in a hardware description language. Higher abstraction languages like C or C++ can be used to describe an algorithm, reducing the risk of errors and also speeding up development. Vivado HLS will not be used per se in this project, but rather the matching pursuit module it has produced in an earlier effort will be imported into Vivado as an external Intellectual Property (IP).
Xilinx Software Development Kit  is the integrated development environment where the programming of the processing system is performed.
It is based on the Eclipse integrated development environment in which C or C++ can be used to write the software running on the Zynq chip’s dual-core CPU. Based on which peripherals in the Zynq-7000 are active and what HDL modules are pro-grammed onto the programmable logic, device drivers with which to control these through software are generated and made available. Interaction between programmable logic and software executing in the processing system is done through custom func-tion calls, defined by said drivers. Other aspects of the CPU are configured at this stage, and XSDK also handles the transferring of the executable program file to the Zedboard.
The processing system and the programmable logic of the Zedboard’s Zynq-7000 chip can be used individually but for this application they will be used in conjunc-tion. Nevertheless, they are programmed separately using different development tools. Section 3.1 describes the programmable logic configuration, section 3.2 the processing system programming. Both sections touch upon the integration of the ADC — the physical and communicative aspect respectively — likewise in the case of the OD1 pump controller.
Programmable logic configuration
The programmable logic configuration and programming of the platform was done using Xilinx Vivado 2015.4 and Xilinx Vivado HLS 2015.4 with the product license obtained through the Zedboard purchase. The matching pursuit HDL module was created in Vivado HLS and imported into Vivado as an Intellectual Property (IP) and integrated with other IPs.
Vivado features an optional design method called a block design. In this graphical user interface, IPs are linked together to be implemented in the programmable logic. An IP is predefined logic that performs particular task, which source code generally cannot be accessed.
Figure 3.1 shows the block design. Rectangles represent IPs and lines represent con-nections in between. In the design there are six modules in total.
ZYNQ7 Processing System.
Vivado’s interface around the processing system of the Zynq and the logic connection between the processing system and the programmable logic. In-put/Output, interrupts, clocks, memory and such are configured with this module.
Matching Pursuit_original (Pre-Production).
This is the matching pursuit module describing the hardware executing the cross-correlation and generating the event table needed to perform the dictio-nary learning.
Two AXI General Purpose Input/Output modules are present, one controlling the inputs and the other monitoring the outputs to the matching pursuit mod-ule.
Processor System Reset & AXI Interconnect.
These modules connect all others with common clock- and reset-lines. These modules are automatically added and connected by Vivado when a ZYNQ7 Processing System module and other IPs are present in the design.
To communicate with external peripherals, the inputs and outputs of the Zynq need to be configured. The platform has two components in addition to the Zedboard, the ADC and the pump controller OD1, both connected to Pmod sockets on the Zed-board. The Zedboard Pmods connect through the Zynq’s Multiplexed Input/Output (MIO) and Extended MIO (EMIO) pins.
The Maxim Santa Fe AFE communicates via an SPI interface. The ADC is connected to the programmable logic through the EMIO pins, via Pmod port JA1 on the Zed-board. EMIO is selected as the SPI’s I/O option, signifying which physical connec-tions will be used to transmit the data.
Lifted from comments in the Maxim Santa Fe firmware  (Code documentation V02.00, sections 5.10.3 & 5.11.2), the Zynq’s SPI clock is set to 114.287513 MHz. When enabled, an SPI bus shows up on the perimeter of the PS7-module in the block design which can be connected to another module accepting it. However, since the ADC is a physical device and not an IP in the block diagram, this connection is made external.
The external signal bus constituting the SPI interface requires routing onto the phys-ical pins of the Zynq for it to connect to the ADC. The Xilinx errata AR# 47511  discloses an error when using SPI with the SS0 signal (spi_1_ss_io) on the Zynq, therefore SS1 (spi_1_ss1_io) is used instead. The Zedboard hardware user’s guide  (section 2.9.2) specifies which pins of the Pmods connect to the pins of the Zynq chip. Each row of the 2×6 pins Pmod has a power pin and a ground pin, hence the exclusion of pins JA- 5, 6 & 11, 12 in the table. The JA Pmod pin mappings onto the Zynq are shown to the left in Figure 3.2. The Maxim Santa Fe Analog Front End documentation  (p. 2) describes the configuration of the ADC pins of the male Pmod header attached to it, denoted J1 in the same Figure 3.2.
Table of contents :
1.1 Matching pursuit with dictionary learning
1.2 Platform specification
1.3 Platform requirements
2 Methods and hardware
2.1 Hardware components
2.2 Protocols and development tools
3.1 Programmable logic configuration
3.1.1 Integrating peripherals
3.2 Processing system software
3.2.1 Interfacing peripherals
4.1 Further work