Performance and Energy Consumption Modeling of Video Decoding 

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Sophisticated embedded operating systems

The increasing complexity of mobile device architectures imposes the use of sophisticated embedded operating systems (EOS) comparable in complexity and functionality to desktop or server ones. In fact, they provide an abstraction mechanism for sharing and managing hardware resources such as processors, storage, multimedia devices and implement almost all standard OS functionalities such as process scheduling, memory management and Input/Output (I/O) support. This central role of the OS in managing mobile devices makes it a very important component to consider when analyzing the energy consumption properties.
From the power consumption viewpoint, the OS is both a source of energy consumption and an energy saving enabler. Indeed, like all the applications running on a mobile device, OS tasks use some part of processing resources and thus contribute in consuming the energy budget [18]. On the other hand, the OS is the component which has the best knowledge of hardware resources utilization which makes it ideal for implementing energy saving policies.
For example, in case of a video application, the OS may be highly involved in the video decoding process to manage the I/O with external video specialized processor (hardware video codec or DSP) or to schedule the decoding over multiple processor cores. These tasks are sources of additional energy consumption. On the other hand, the OS is able to save energy by idling the processors or lowering its frequency during low activity periods in the video decoding process.

Problem statement : Energy consumption modeling of processor-based video systems

In general, an energy model allows understanding and predicting the energy consumption in terms of well identied factors or parameters. Understanding how much a given parameter impacts the energy consumption can help in tuning it to reduce the consumed energy. This is especially true when the eects of interactions between the dierent parameters are understood. On the other hand, the prediction of the amount of consumed energy is extremely useful to dimension the energy budget and estimate the autonomy. As highlighted previously, the processing resources are a major source of energy consumption in the context of video decoding applications. However, in case of complex processor-based system, well understanding the energy consumption properties should consider in addition to the processing resources, the executed operating system and applications. For example, the above sections show that the energy consumption considerations of video applications are present across dierent mobile device components. Ideally, an energy model for the above described systems should consider all the relevant parameters and should estimate accordingly the consumed energy accurately.
However, in practice, this is hard to achieve for complex systems and these objectives may be fullled partially. Actually, realistic energy consumption models for complex system can consider only a subset of parameters. On the other hand, they may induce some errors in their predictions as compared to real energy consumption values. The questions which can raise is how to select the most relevant parameters and how to make the developed model as accurate as possible? Answering these questions depend mainly on the considered abstraction level of the targeted system. As we will discuss hereafter, there exist two main approaches: 1) Low level modeling and 2) High level modeling.

Energy characterization methodology

A performance and energy characterization of video decoding was achieved based on an extensive experimental measurement methodology. In these experimentations , single core and multi-core ARM processors, DSP and hardware video codecs architectures were considered. On these dierent processor architectures, the processor frequency and video quality (Standard Denition (SD) and High Denition (HD) quality) parameters were considered.
An extensive characterization achieved on GPP and DSP processors for decoding SD video quality revealed that the performance-energy trade-o highly depends on the decoded video quality and the type of processor architecture. It was highlighted that the scheduling overhead over heterogeneous processor impacts the energy eciency of video decoding when achieved on external specialized processor. Thus, depending on the video quality, it may be more energy ecient to decode a video on a GPP rather than a DSP. This contribution is published in [22, 5].
On the other hand, a performance and an energy characterization of HD video decoding on various processing conguration including of mono-core, multi-core GPP and hardware codec was achieved. It was shown that parallel HD video decoding on multi-core processors reduces considerably the gap between the energy consumption of hardware accelerated decoder and software-based ones. It is thus an interesting solution achieving a balance between the software exibility and hardware codec energy eciency. This contribution is published in [24].

Energy modeling methodology

Based on the results of the performance and the energy characterization of video decoding on GPP (ARM) and DSP, it was proposed:
A performance analytical model for video decoding which considers both clock frequency and video quality parameters. This model describes also the impact of the o-chip memory access latency on performance variation of video decoding when varying the processor clock frequency. This contribution is published in [25].
An energy consumption model for video decoding which estimates analytically the consumed energy as a function of the processor clock frequency, the video bit-rate and a set of comprehensive architecture, system and video related parameters. The developed model has a very good energy consumption prediction properties (R2 = 97%) for the two type of processors. This contribution is published in [25].
A methodology to generalize and port the proposed energy model to other ARM processor architectures. This contribution is published in [26].

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Table of contents :

List of Figures
List of Tables
List of Abbreviations & Notations
List of Publications
1 Introduction 
1.1 Context
1.1.1 Increase in mobile devices power consumption
1.1.2 New trends in mobile video applications usage : Implications on power consumption
1.1.2.1 Increase in mobile video trac
1.1.2.2 Ubiquitous video applications
1.1.3 Complex multimedia mobile devices
1.1.3.1 Multi-core and heterogeneous processing
1.1.3.2 Sophisticated embedded operating systems
1.2 Problem statement : Energy consumption modeling of processor-based video systems
1.2.1 Low level modeling
1.2.2 High level modeling
1.3 Thesis scope and approach
1.4 Thesis contributions
1.4.1 Experimental methodology
1.4.2 Energy characterization methodology
1.4.3 Energy modeling methodology
1.4.4 Applications
1.5 Outline
2 Background and related works 
2.1 Introduction
2.2 Background
2.2.1 Concepts on video encoding and decoding
2.2.1.1 Principles of MPEG standards
2.2.1.2 Video quality assessment metrics
2.2.1.3 Video playback QoS assessment metrics
Deadline miss rate (DMR)
Decoded frames per second (FPS)
Latency
2.2.2 Energy consumption in electronic circuits
2.2.2.1 Static vs dynamic energy consumption
2.2.2.2 Dynamic voltage and frequency scaling (DVFS)
2.2.2.3 Dynamic Power management (DPM)
2.2.3 Discussion
2.3 Principles of energy saving in video decoding
2.3.1 Frequency scaling: Performance vs energy consumption
2.3.1.1 Frame-by-frame based DVFS
2.3.1.2 Average workload based DVFS
2.3.1.3 Video-aware DVFS : Challenges and issues
2.3.2 Parallel multi-core video decoding
2.3.3 Specialized processing
2.3.3.1 Hardware video codecs
2.3.3.2 Graphical processing unit
2.3.3.3 Digital signal processor
2.3.4 Discussion
2.4 Performances and energy consumption characterization of video decoding
2.4.1 Video decoding performances characterization
2.4.1.1 Application level
2.4.1.2 System level
2.4.1.3 Architecture level
2.4.2 Video decoding energy consumption characterization
2.4.2.1 Application level
2.4.2.2 System level
2.4.2.3 Architecture level
2.4.3 Discussion
2.5 Performances and energy consumption modeling of video decoding
2.5.1 Video decoding performances modeling
2.5.1.1 Frame based models
Empirical models
Metadata-based models
2.5.1.2 Interval-based models
2.5.1.3 Memory-aware performance models
2.5.2 Video decoding energy consumption modeling
2.5.2.1 Application level
2.5.2.2 System level
2.5.2.3 Architecture level
2.5.3 Discussion
2.6 Conclusions
3 Methodology 
3.1 Introduction
3.2 Characterization methodology
3.2.1 Video complexity characterization
3.2.2 Operating-system level characterization
3.2.3 Video-frame level characterization
3.2.4 Video sequence level characterization
3.3 Modeling methodology
3.3.1 Video rate Sub-model
3.3.2 Power sub-model
3.3.3 Decoding-time sub-model
3.3.4 Models validation
3.4 Experimental methodology
3.4.1 Hardware setup
3.4.1.1 MistralEVM3530
3.4.1.2 PandaBoard
3.4.2 Power consumption measurement
3.4.2.1 Open-PEOPLE platform
3.4.2.2 Power consumption measurement methodology
3.4.2.3 Boards instrumentation
3.4.3 Software setup
3.4.3.1 Video encoder
3.4.3.2 Operating system
Dynamic power management
Frequency scaling
3.4.3.3 Video decoder framework
Elimination of the I/O interference
Overhead calculation
3.5 Conclusion
4 Performance and Energy Consumption Characterization 
4.1 Introduction
4.2 Video complexity characterization
4.3 Video decoding performance and energy characterization
4.3.1 Operating-system level
4.3.1.1 ARM processor
4.3.1.2 DSP processor
4.3.1.3 C-states transition overhead
4.3.2 Video-frame level
4.3.2.1 Inter-processor communication time overhead
4.3.2.2 Inter-processor communication energy overhead
4.3.2.3 Discussion
4.3.3 Video-sequence level
4.3.3.1 Decoding time
4.3.3.2 Power consumption
4.3.3.3 Energy consumption
4.3.3.4 Discussion
4.4 Conclusion
5 Performance and Energy Consumption Modeling of Video Decoding 
5.1 Introduction
5.2 Video rate sub-model
5.2.1 Parameters discussion
5.3 Power sub-model
5.3.1 Static power sub-model
5.3.2 Dynamic power sub-model
5.3.2.1 ARM video decoding
5.3.2.2 DSP video decoding
5.3.2.3 Dynamic power modeling
5.3.3 Parameters discussion
5.4 Decoding time sub-model
5.4.1 Parameters discussion
5.5 Energy model
5.6 Models validation
5.6.1 Models accuracy on OMAP3530
5.6.1.1 Decoding time model
5.6.1.2 Energy model
5.6.2 Models generalization: OMAP4460 SoC case study
5.6.2.1 Decoding time model
5.6.2.2 Energy model
5.7 Conclusion
6 Applications and open issues 
6.1 Introduction
6.2 Energy-aware video decoding in adaptive streaming
6.2.1 Motivational example
6.2.2 Energy aware scheduling of video decoding on heterogeneous multi-core SoCs
6.2.2.1 Principles
6.2.2.2 Implementation
6.2.2.3 Evaluation
6.2.3 Video-quality aware DVFS
6.2.3.1 Problem description
6.2.3.2 Proposed solution
6.3 Energy eciency of high denition video decoding
6.3.1 Motivation
6.3.2 Experimental evaluation
6.3.2.1 Hardware and software setup
6.3.2.2 Performance measurement
6.3.2.3 Energy consumption measurement
6.3.3 Experimental results
6.3.3.1 Video decoding performances
6.3.3.2 Video decoding energy consumption
6.4 Discussion
6.4.1 Per-core frequency scaling
6.4.2 Processing migration on asymmetric multi-cores
6.5 Conclusion
7 Conclusions and future works 
Bibliography

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