SST topologies for DC power distribution systems

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SST topologies for DC power distribution systems

There are several prominent topologies for SST applications, from two-level converters to the multilevel converters, which focus around different applications, topologies, power devices requirements, among others. Examples can be found in Zhao et al. (2013), She et al. (2013), Madhusoodhanan et al. (2015), and Barreto et al. (2018). However, since each SST application brings different characteristics to the table, this topic concentrates the attention in review studies focusing on DC power distribution systems, like the ones presented by She et al. (2012) and Rodriguez et al. (2017).
The multilevel converters have already been recognized as a good option for several medium- and high-voltage industrial applications, and they can be used into the SST conversion stages. Compared to two-level converters, they allow for an increase in the number of voltage levels at the output, which allows the reduction of the harmonic content and, consequently, the filter elements. The most well-known topologies are: NPC (Neutral-Point Clamped) (Figure 1.3a), FC (Flying Capacitor) (Figure 1.3b) and CHB (Cascaded H-Bridge) (Figure 1.3c). Also, other features are provided, as they allow a voltage rise without the need for step-up transformers, high efficiency, voltage and current efforts reduction on semiconductor devices, common mode voltage elimination, among others (SADIGH; DARGAHI; CORZINE, 2015).

HVS modulation technique

A HVS modulation must be developed to obtain the desired virtual voltages (ve and vt), which are respectively related to the input voltage van and MFT primary voltage vp, in each phase.
Among the possible techniques (DEBNATH et al., 2015) (KONSTANTINOU; CIOBOTARU; AGELIDIS, 2013) (PICAS et al., 2015) (DENG et al., 2016), the adopted modulation technique is based on the space vector modulation. According to the number of submodules N present in each arm, the implementation begins by listing all the possible switching states in terms of the ve and vt voltages. This is possible since ve and vt are directly related to the submodules switching states by equations (2.16) and (2.17). Assuming 4 submodules per arm, the resulting space-state diagram is shown in Figure 2.8. The switching states are divided into sectors. One sector corresponds to a given level of ve. Thus, the operation of the vector sequence follows the same pattern for all sectors. 2.5 LVS modulation technique At the LVS, the choice of the modulation technique took into account that the fullbridge converter provides the maximum of three voltage levels in the MFT secondary voltage. Thus, the SHE-PWM (Selective Harmonic Elimination Pulse-Width Modulation) was chosen to suppress the third order harmonic component (and its multiples), due to it being the one with the smaller order, which enables the reduction of MFT voltage and current stresses (SANCHEZ-RUIZ et al., 2017).


Capacitors voltage balancing and circulating currents minimization algorithm

As for any modular multilevel converter, the submodules capacitor voltage balancing is mandatory for its functional operation (GHETTI et al., 2017). From (2.23), it is observed that the circulating currents derivatives changes according to nx, ny and vbus. If vbus is kept regulated by the control system, by setting the number of active submodules in each leg nx and ny, it is possible to change the direction of the circulating current in order to minimize it. For that, since the average bus voltage vbus is nearly equal to NVc, the following equations must be respected
 If the circulating current is increasing, the number of active submodules in each leg (nx and ny) must be higher than N;
 If the circulating current is falling, the number of active submodules in each leg (nx and ny) must be lower than N. From that, the capacitors voltage balancing (CVB) and the circulating currents minimization (CCM) can be combined together in a single algorithm (CVB/CCM), as illustrated in Figure 2.11. This is one important specificity of this converter. The algorithm is used in each leg and the steps are described as follows:

Table of contents :

1.1 Context
1.2 SST concepts
1.3 SST topologies for DC power distribution systems
1.4 Motivation and constraints
1.5 Thesis objectives
1.6 Outline
2.1 Structure
2.2 Principle of operation
2.3 HVS Modeling
2.3.1 Leg mid-point voltages vxn and vyn
2.3.2 Input voltage van and MFT primary voltage vp
2.3.3 Bus voltage vbus
2.4 HVS modulation technique
2.5 LVS modulation technique
2.7 Control scheme
2.7.1 HVS plant
2.7.2 LVS plant
2.7.3 HVS and LVS control scheme
2.8 Final comments
3.1 Converter analysis
3.1.1 Optimum number of submodules per arm Nopt
3.1.2 Optimum transformer turns ratio kopt
3.1.3 RMS value and THD of the voltage vt
3.1.4 Losses
3.2 Design
3.2.1 Input inductor Lg
3.2.2 Arm inductor L
3.2.3 Submodule capacitor C
3.2.4 Bus capacitors Cb1 and Cb2
3.2.5 Medium-frequency transformer
3.2.6 Output capacitor Co
3.3 Simulation
3.3.1 Steady-state operation
3.3.2 Power flow inversion operation
3.4 Final comments
4.1 Prototype specifications and overview
4.1.1 Overview of the prototype
4.1.2 Overview of one submodule
4.1.3 Overview of the arm FPGA
4.1.4 Overview of the master FPGA
4.2 Experimental results
4.2.1 Steady-state operation
4.2.2 Dynamic operation
4.3 Final comments
5.1 Scientific production
5.1.1 Proceedings papers
5.1.2 Journal papers


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