State-of-Art SDR Transceiver Architectures

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Receiver Architectures

The receiver (RX) is a crucially sensitive part in a RF transceiver, making it likely the most challenging to design. The performance of the RX is set by the Signal-to-Noise ratio (SNR) at the input of the ADC. The SNR depends on the chain’s gain, lters’ performance and will ultimately determine the achievable Bit Error Rate (BER). Other aspects that have to be considered during the design process are: footprint size, production cost, power consumption, multiband capabilities, single-chip integration, etc. Each architecture represents a compromise between these dierent factors. In the following subsections, the main RX architectures are described.

Heterodyne Architecture

The heterodyne (or superheterodyne) architecture is often the best choice for delivering high performance and high gain (>75 dB, which is usually required by military applications). The idea behind the heterodyne RX chain is to amplify the desired RF band by as much as 120 dB, to recover the transmitting channel from noise and interference, through several stages. The rst obstacle is to reject adjacent (and unwanted) signals known as blockers, by the use of a band-selection lter close to the antenna. At the output of this stage, there remains only the desired band, contaminated only by wideband noise. The heterodyne architecture is shown in signals through the amplication stage done by a Low-Noise Amplier (LNA).
The second down conversion to BB is done by means of two channels, Inphase (I) and quadrature (Q). The split is necessary because it is not possible to detect a general IF signal, simultaneously modulated in both amplitude and phase using a single path. The split IQ quadrature architecture is not mandatory for AM and FM signals. However, the exibility and the control achievable with IQ channels, makes it desirable for most modern radio. The quadrature architecture is therefore a \de rigueur » for every SDR transceiver. The advantages and the drawbacks of the heterodyne receiver are summed up in Table 3.1. What it is important to retain is that the heterodyne architecture can provide reliable performance at the expense of the high power, complexity and reduced exibility.

Homodyne Architecture

The main concern of a heterodyne receiver is the management of the image frequencies spaced from the desired frequency by twice the IF. One possible solution is to set the IF to DC and shift the desired channel directly to baseband.
Designed as a simplied version of the heterodyne receiver, the homodyne (or Zero IF) receiver translate the desired signal directly to BB through the I and Q channels (Fig. 3.3). This receiver consists of an LNA which provides modest RF gain at a low noise gure. The output of the mixer is ltered in a bandpass pre-selection lter, and down-converted in a complex IQ mixer. The IQ quadrature architecture is mandatory in the homodyne transmitter, since mixing a general RF signal signal to zero IF frequency with a single-channel architecture would produce non-recoverable aliasing [Schwartz, 1980].
As explained, the homodyne RX doesn’t have to worry about image frequency interference, thus no highly selective bandpass lters are needed. It only requires Nyquist-band anti-aliasing LP lters ahead of the ADCs, a much simpler design problem. This makes the homodyne architecture suitable for IC integration. However, a whole new set of issues appear. Because the IF lter is absent, all the shielding from close interferers must come from the I and Q lowpass lters. Furthermore, the mixer needs to operate over a wide frequency band. In comparison, the heterodyne RX works at a xed frequency. Nonetheless, because of its exibility and high level of integrability the homodyne architecture is suitable for applications that aim at multiband operation and can tolerate loss in sensitivity. The advantages and the drawbacks of the homodyne RX receiver are summarized in Table 3.1.

Low IF Receiver

A candidate architecture that tries to combine the advantages of the homodyne and heterodyne RX is the low IF RX [Adiseno et al., 2002], in which the RF signal is mixed to nonzero low or moderate IF (few hundreds of KHz to several MHz). Similarly to the homodyne structure, the RF signal is passed through a channel-selection lter and amplied by a LNA (Fig. 3.4). However, after this step, the signal is down-converted to low IF instead of zero IF. An image suppression bank of lters is used in order to cancel the negative eects from the frequency image. Finally, the ADCs convert the low IF signal to digital domain, where digital signal processing algorithms are used. In some low IF architectures the image suppression block is transferred to the digital domain.
The architecture still allows a high level of integration but does not suer from DC problems, since the signal of interest is not situated around DC anymore. Nonetheless, the low IF architecture still suers from the image frequency and I/Q mismatch problems. Further more, the ADC power consumption is increased since now a higher conversion rate is required. The advantages and the drawbacks of the low IF receiver are summarized in Table 3.1.

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Receiver Architectures. Comparison and Conclusions.

Over the years, several RX architectures have been introduced, and this evolution has been guided by the fabrication technology available, the wireless standards addressed and the markets served. The spectacular gain in speed and level of integration is inexorably pushing the eld to newer \digitally-assisted » architectures. Despite this trend, the best performing RX frontends still fall in three types: heterodyne, homodyne, and low IF. Military radio units place range (i.e. sensitivity) above all else, making the heterodyne architecture the most common choice. Nonetheless, newer products must inter-operate with civilians wireless standard, such as 4G or 5G, so new \hybrid » designs are needed. These forthcoming products will need more sophisticated test strategies, covering all signal paths.

Table of contents :

Abstract
Resume
Contents
Symbols & Abbrevations
List of Figures
1 Introduction 
1.1 Background
1.2 Previous Work
1.3 Our Work
1.4 Research Contributions
1.5 Thesis Organisation
2 Resume (Francais) 
2.1 Introduction
2.2 Radio logicielle
2.3 Test RF
2.3.1 Test et testabilite des systemes electroniques
2.3.2 Des dans le test des systemes RF
2.3.3 Etat de l’art du domaine de testabilite des systemes RF
2.3.4 Conclusions
2.4 Application de la technique de sous-echantillonnage non-uniforme au test integre des emetteurs RF exibles
2.4.1 Introduction
2.4.2 Outil theoriques
2.4.3 Description generale de l’architecture de test
2.4.4 Resultats en simulation
2.4.5 Conclusions et perspectives
3 Software Dened Radio 
3.1 Introduction
3.2 Some History
3.3 What is an SDR
3.4 SDR Architectures
3.4.1 Receiver Architectures
3.4.2 Transmitter Architectures
3.4.3 State-of-Art SDR Transceiver Architectures
3.5 Transceiver Specications
3.5.1 Small-signal FoMs
3.5.2 Signal Power FoMs
3.5.3 Distortion FoMs
3.5.4 Noise Specications
3.5.5 Digital FoMs
3.5.6 Final Remarks on FoMs for RF Transceivers
3.6 Conclusions
4 RF Testing 
4.1 Test & Testability of Electronic Systems
4.1.1 Test Classication
4.2 Challenges in AMS/RF Testing
4.3 Automated Test Equipments
4.4 Built-In Self-Test
4.4.1 Loopback BIST
4.4.2 Behavioral RF Modeling
4.4.3 Model-Based RF Test Strategies
4.4.4 Alternate Tests
4.5 Conclusions
5 Undersampling 
5.1 Introduction
5.2 Nyquist Sampling
5.3 Bandpass Sampling Techniques
5.3.1 Classic Undersampling
5.3.2 Periodical Nonuniform Sampling of Second Order (PNS2)
5.3.3 Noise Degradation in Undersampling Techniques
5.4 Conclusions
6 SDR Test Strategy 
6.1 Introduction
6.2 General Description of the Proposed Test Architecture
6.3 Digital PNS2 Reconstruction
6.3.1 FIR Implementation
6.3.2 Kaiser Window
6.3.3 Alternatives & Other Considerations
6.4 Delay Generation Block
6.4.1 Choice of D
6.4.2 Reconstruction Robustness w.r.t. Uncertainties in D
6.4.3 DCDE Practical Implementation
6.4.4 Delay Estimation
6.5 Sample and Hold Elements
6.5.1 Charge-domain sampling
6.5.2 Improved BIST Architecture Based on CBS
6.6 Simulation Results
6.6.1 General Simulation Parameters
6.6.2 Adjacent Channel Power Ratio estimation
6.6.3 Digital PNS2 Reconstruction
6.6.4 Analysis of Time-Skew Detection Techniques
6.6.5 ACPR Simulation
6.7 Conclusions
7 Conclusions and Future Work 
7.1 Conclusions
7.2 Future Work
Bibliography

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