Structure of a Microprocessor’s PDN

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Chapter 3 Feasibility Study

A bi-pronged approach for determining the feasibility of the microprocessor level PLC scheme was adopted. The first approach was to develop high-frequency models of the PDN of a microprocessor and study the frequency response of the PDN thus obtained. This approach has been presented in the first part of the chapter. The other approach was to measure frequency characteristics of an actual microprocessor’s PDN. Undertaking these measurements was not straight-forward due to practical issues involved, as explained later in this chapter. The second approach, supposed to verify the results of analytical approach, showed complete divergence from the analytical models. However, the measurements still supported feasibility of the PLC scheme, which has also been verified through system level modeling, presented in the next chapter.

Feasibility Study Using PDN Models

This section elaborates the approach followed for modeling the PDN. Specifically, models for each individual components of PDN are described. Finally, these models are combined together to study the frequency response of a generic microprocessor’s PDN. Based upon the microprocessor level PLC scheme, illustrated in Figure 1.1, the communication path goes through microprocessor socket pins, package power and ground pin, package planes, chip I/O (C4 bumps and solder balls) and finally to IC level power grid. The following sub-sections discuss models employed for each of these PDN components.

Model for Power/Ground Pins of a Socket or a Package

The socket and package power and ground pins can be modeled with good accuracy using a series lumped resistor and inductor model [20]. Due to the presence of a large number of power and ground pins, supplying and sinking currents in parallel, the effective resistance and inductance of package pins is quite low. The effective inductance is less than a few pH and the effective resistance is less than a mΩ. This small inductance is inconsequential, considering the inductance of package power and ground planes and hence is neglected in order to simplify the analysis of the PDN [21]. Moreover, the resistance of socket/package pins is an important concern only while considering IR voltage drop. However, it can also be neglected in our analysis, where the signal power involved is small.

Package Plane Model

It has been indicated that the use of lumped element models for modeling PDN components, especially for package power planes, is unable to capture PDN frequency characteristics accurately at frequencies above 1 GHz [22]. At GHz frequencies wave propagation and edge effects from power distribution planes becomes a dominant factor impacting frequency characteristics of PDNs. Numerical methods can be applied to analyze such structures [23], however, using such techniques to construct broadband models valid up to GHz of frequency range becomes computationally very intensive. In [22], physics based model called Cavity Resonator Model has been proposed for modeling power planes. Power planes are considered as a resonant cavity connected to electrical ports located arbitrarily on the planes and are characterized by a modal N-port impedance (Z) matrix. Figure 3.1 illustrates the CRM model. The figure shows two power planes with 2 ports i and j being modeled with a 2-port impedance The model has been shown to be computationally efficient and accurate for high frequency modeling of power planes [21].
The impedance equation is based upon the assumptions that a, b >> d and d << λ (wavelength), where a x b are the dimensions of the power planes and d is the distance between them. m and n are the propagating modes. δ is the dielectric loss angle, and εm and εn = 1 for m, n = 0 and  2 otherwise. (xi, yi) and (xj, yj) are the coordinates of the port locations and (txi, tyi) and (txj, tyj) are the dimensions of port i and j. ωmn = 2πfmn, where fmn is the resonant frequency of each mode.
The spice equivalent circuit based upon CRM model of two power planes with N arbitrarily located ports is shown in Figure 3.2.

Solder Ball and C4 Bump Models

Solder balls and C4 bumps can be accurately modeled using lumped elements because of their small sizes. A series resistor with an inductor models solder balls or C4 bumps accurately [20]. Due to small size of solder balls and C4 bumps, their parasitic inductance and resistance is quite small, even smaller than those of package/socket pins. Moreover, effective parasitic impedance of power and ground bumps is further reduced due to the use of a large number of power and ground bumps in a microprocessor die. Based upon the reasoning given in section 3.1.1, the parasitic of solder balls and C4 bumps are neglected in our analysis.

IC Level Power Grid Model

In order to estimate the delay and attenuation at various locations in a microprocessor chip, a distributed model of the on-chip power grid is required. A simple and widely used distributed RLC model is employed in our analysis. In the distributed RLC model, the die area is divided into a grid of cells. Each cell is then reduced to a simplified RLC macromodel. These macromodels combine together to form a RLC grid model of the on-chip power grid, as shown in Figure 3.3. RLC extraction for each macrocell is carried out using the procedure explained in the following paragraphs.
Resistive component of a metal wire can be calculated using the formula given in equation (2), where the metal trace length depends upon the macrocell size. Metal trace width calculation involves an iterative procedure [24], [25]. The goal of this iterative procedure is to estimate the minimum number of power pads, their placement and the minimum width for power trace routings, in order to reduce the IR voltage drop at any location in the die. Final IR voltage drop at any location in the die should lie within the design specifications.

Case-Study: Modeling PDN of a Microprocessor Die Packaged in a FC-PGA Package

Models of various PDN components, described in previous sub-sections, were combined together and used to model the PDN of a microprocessor die packed in Flip Chip Pin Grid Array Package (FC-PGA) package. The design parameters, such as chip dimension, number of power pins (or balls), package were selected for constructing a generic integrated circuit whose specifications are comparable to a high performance microprocessor. The selection was carefully done in order to avoid landing-up with an extremely huge netlist which will be hard to simulate using the university compute resources. The design parameters are enlisted below:
Package model parameters:

  • Package dimension: 20 mm × 20 mm.
  • Number of pins: 400.
  • Number of power pins: 100.
  • Number of ground pins: 100.
  • Number of signal pins: 200.
  • PDN model parameters:
  • Chip dimension: 10 mm × 10 mm (More accurately, 9999.96 μm × 9999.96 μm).
  • Number of power cross points: 100 (10 and 10 wires in M4 and M5, respectively).
  • Metals for power bus: M4 and M5.
  • Sheet resistance for M5: R = 0.04 Ω/sq.
  • Sheet resistance for M4: R = 0.07 Ω/sq.
  • Via resistance (Rvia) for the interconnection between M4 and M5 = 8.68 Ω.

The necessary parameters for RLC parasitic computation were extracted from TSMC 0.25 um process technology. Also, FR4 was assumed as the material used in the package substrate. Note that we have modeled only power mesh of the on-chip power grid because we are interested in analyzing signal propagation through the power line. Figure 3.4 illustrates the simulation setup.
The point of application of UWB impulse through the package pin (P1) is highlighted in the figure. Also, the point of reception of the impulse inside the chip (P2) is indicated. It is assumed that the receivers of microprocessor level PLC can be placed close to the chip power pads, therefore P2 is placed at location n1v1 marked on the distributed RLC model of on-chip PDN.

1. Introduction 
1.1 Motivation
1.2 Power Line Communications in Microprocessors
1.3 Contributions of this thesis
1.4 Thesis Organization
2. Preliminaries
2.1 UWB
2.2 Direct Sequence Spread Spectrum
2.3 Structure of a Microprocessor’s PDN
2.4 Chapter summary
3. Feasibility Study 
3.1 Feasibility Study Using PDN Models
3.2 Feasibility Study through Measurements on PDN
3.3 Chapter Summary
4. System Level Study 
4.1 Simulated System Model
4.2 MATLAB Simulation Results
4.3 Significant Findings
4.4 Chapter Summary
5. Data Recovery Block Design
5.1 Architecture
5.2 Circuit design
5.3 Performance Evaluation
5.4 Test Chip Implementation
5.5 Fabrication Results
5.6 Chapter Summary
6. Conclusion and Future Work 
6.1 Conclusion
6.2 Applications
6.3 Future Work
Bibliography
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Power Line Communications in Microprocessors – System Level Study and Circuit Design

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