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Actives elements in SOI CMOS 65nm
In comparison to other technologies, CMOS is the most cost-effective solution to date for large scale digital applications and it enables ultra high level system-on-a-chip integration. Driven by high performance digital applications, high frequency performances in silicon technology have considerably increased with geometry scaling. Non digital figure of merits, such as fT, fmax or NFmin show that silicon transistors become competitive with III-V transistors [1]. This chapter is built as follows. First, transistor RF figures of merit are discussed, then high frequency small signal model of the MOSFET transistor is presented. Next, the noise sources and their modeling in MOSFET transistors are developed. After that, SOI MOSFET characterization is presented and performances of the CMOS SOI and bulk 65nm technologies are compared with the state of the art. Finally, BSIM MOSFET model are detailed.
Transistor RF figures of merit
The two most important features of transistor are its ability to amplify (important for analog and RF) and its ability to act as a switch (important for digital electronics and mixers). These two characteristics are evaluated using the gain definition for analog RF and the Ion/Ioff performances for digital electronics. Today CMOS technologies have to deal with these two important figures of merits. Unilateral gain is used to evaluate the figure of merit fmax. The maximum oscillation frequency is the frequency at which the unilateral power gain is equal to 1. The current gain is used to evaluate the figure of merit fT. The device fT is the frequency at which the short circuit current gain falls to unity (0dB). In this work, transistors are evaluated using the maximum stable gain (MSG), the maximum available gain (MAG), the unilateral power gain or Mason gain (U), the current gain (H21) and the associated gain (Gass) All these gain definitions are given in appendix.
Chapter II.
High Frequency small signal model of the SOI MOSFET transistor
One of the advantages of SOI transistors compared to bulk devices is that at millimeter wave frequencies, the substrate does not impact significantly the behaviour of transistors. Thanks to the thickness of the buried oxide, the body effect can be neglected at high frequency [2]. Thus, it is not necessary to develop a four terminal model for the SOI floating body transistor used at RF and millimeter wave frequencies. In the next two sections, a general small signal equivalent circuit of floating body SOI MOSFETs is presented, taking into account its intrinsic behavior and its physical structure. The model extraction methodology is not discussed here. The complete description of this methodology is given in [3] and [4]. An example of extracted small signal circuit elements is given in appendix.
Quasi static model
Small signal or linear models are used to evaluate the stability, gain, noise and bandwidth of designed circuits. A small-signal model is generated by taking derivatives of the current-voltage curves at biasing point. As long as the signal is small relative to the nonlinearity of the device, the derivatives do not vary significantly, and can be treated as standard linear circuit elements. A big advantage of small signal models is they can be solved directly, while large signal nonlinear models are generally solved iteratively, with possible numeric convergence or stability issues. Figure II.1 Intrinsic quasi static small signal model of a (SOI) MOSFET To get an understanding of the high-frequency properties of a MOSFET and to analyze them, the equivalent circuit should be simplified a lot. Quasi-static behavior of the channel charge is assumed under the hypothesis that the electron channel transit time is negligibly small. The transcapacitances are also neglected. Figure II.1 described the intrinsic quasi static model of the MOSFET. The bulk or substrate node has been neglected as explain previously (not necessary in SOI) as well as the gmbs, Cgb and RB components. The transistor geometry affects each device terminals by capacitive coupling and can be modeled by capacitances added in the equivalent circuit as shown in Figure II.1. All these components are bias dependent and are related to variations of charges or currents when a small signal is applied around equilibrium on a terminal.
These relations can be used only in quasi-static operation. The applied small signal is varying slowly enough such as the charges respond instantaneously to the applied signal. The capacitances are the representations of the influence on the charges of a voltage applied on a terminal, with regards to the MOSFET physic. They are called intrinsic capacitances. Moreover, MOSFETs are imperfect current sources, thus an output conductance must be added in the model.
Non quasi static model
In the previous section, a MOSFET equivalent circuit has been presented, considering that charges respond without delay to the applied signal. But when the frequency increases, the charges are not able to follow the signal instantaneously. According to Tsividis, the frequency upper limit of the quasi-static model is proportional to 1/L2, where L is the channel length of the transistor [5]. To model the non-quasi-static effects, the MOSFET channel can be divided into several small transistors connected together. Then, quasi-static models are used for all sub-transistors. This solution can be used when the values of the intrinsic elements are obtained using formulae from the physical model. If they have to be extracted from measurements, this method cannot be used, because the number of unknowns becomes too high. Instead of dividing the MOSFET into several small transistors, the non-quasi-static effects can be modeled by introducing new elements in the equivalent circuit (Ri, Rgd and a time delay (τ) affecting the transconductance) [5]. These elements are represented in Figure II.2. The command of the voltage controlled current source is still the potential “Vgsi”applied to the intrinsic capacitance Cgs.
The extrinsic gate to source (Cgse), gate to drain (Cgde) and drain to source (Cdse) capacitances (not shown in schematic) are included into Cgs, Cgd and Cds. They come from two different causes: · Cgse and Cgde include overlap capacitances, located between the gate oxide and the source and drain diffusion under the gate. They also include the fringing capacitances from the gate sides to the source and drain implants. · The capacitance Cdse is completely different from the two other extrinsic capacitances. It is the expression of the coupling between source and drain through the film of silicon, the buried oxide and the substrate.
Extrinsic parasitic access models
The intrinsic gate, source and drain are connected to the Metal one of the BEOL1 by the gate, source and drain finger contacts (also called CO). These fingers and contacts have a given resistivity. They are distributed elements but since the transistor is generally small compared to the wave length they are modeled by using lumped resistances called Rg , Rs and Rd connected to the gate, the source, and the drain respectively (Figure II.2). The resistances Rd and Rs include the metallic losses and the contact resistances between the metal and the source and drain implants. They are proportional to the inverse of the transistor width. The resistance Rg includes the resistance of the gate fingers, which is proportional to the transistor width, and the resistance of the contacts and metallic lines. In 1 Back End Of Line most of the cases, the resistance of the gate finger is much higher than the others.
With is R□ is the material sheet resistance, Nf is the number of fingers, ga is the number of gate accesses (1 or 2), XGW the distance between the gate contacts and the active part of the transistor, L and Wf the length and the width of a unit finger and Rcont and Ncont the contact resistance and the number of contacts respectively.
Using the same methodology, parasitic inductances can be defined. They are called Lg, Ld and Ls in Figure II.2. For sub-micron MOSFETs, these inductances are usually a few pico Henry (up to metal one) and are nearly negligible within the frequency band of operation. Finally the capacitances Ccg and Ccd represent the contact metallic interconnection capacitances from the gate and the drain.
Table of contents :
Introduction
Chapter I – The CMOS Silicon On Insulator Technology
5 I.1. The SOI Substrate
6 I.2. MOSFET transistor on bulk and SOI
I.2.1. Comparison between bulk and SOI MOSFET
I.2.1.a. Benefits of the SOI technology
I.3. Properties and Behavior of SOI MOSFET
I.3.1. Comparison and properties of Fully and Partially Depleted SOI MOSFET
I.3.2. Floating Body effects
I.3.2.a. The kink effect
I.3.2.b. Parasitic open based NPN bipolar effect in FD SOI MOSFET
I.3.3. Which SOI Device for which design?
I.4. FB and BC MOSFET from the CMOS SOI 65nm technology
I.4.1. Which PD SOI MOSFET for which design?
I.5. Summary
I.6. Bibliography
Chapter II – Actives elements in SOI CMOS 65nm
II.1. Transistor RF figures of merit
II.2. High Frequency small signal model of the SOI MOSFET transistor
II.2.1. Quasi static model
II.2.2. Non quasi static model
II.2.2.a. Extrinsic parasitic access models
II.2.2.b. fT, fmax figures of merit from small signal model
II.3. Noise analysis of the MOSFET transistor
II.3.1. Flicker Noise
II.3.2. Thermal noise
II.3.3. Thermal noise from access resistances
II.4. Noise temperatures
II.4.1. High Frequency noise measurements and associated models
II.5. SOI MOSFET characterization
II.5.1. DC performances
II.5.2. RF performances
II.6. CMOS Transistors State of the Art
II.7. MOSFET Transistor Models
II.7.1.a. BSIM3 SOI Model
II.7.2. BSIM4 model
II.8. Summary
II.9. Bibliography
II.10. Appendixes:
Chapter III – Passive elements in SOI CMOS 65nm
III.1. Passive elements for RF and Millimeter wave frequencies
III.1.1. Passives elements states of the art in industrial silicon technology
III.1.2. Interconnects in 65nm SOI CMOS technology
III.1.2.a. Multi-layer constraints of integration
III.1.3. Lumped or distributed circuit elements?
III.1.3.a. Working Frequency
III.1.3.b. Self Resonant Frequency
III.1.3.c. Current Density
III.1.4. Inductors in SOI CMOS technology
III.1.4.a. SOI Inductors for RF applications
III.1.4.b. Millimeter Wave Inductance
III.1.5. MOM Capacitor in SOI CMOS technology
III.1.6. Waveguide components on silicon substrate
III.1.6.a. Transmission Lines
III.1.6.b. Thin Film Microstrip Line
III.1.6.c. Coplanar Waveguide
III.2. Passive elements characterization
III.2.1. De-embedding methodology
III.2.1.a. Open Circuit de-embedding
III.2.1.b. Open-Short Circuit De-embedding
III.2.1.c. De-Embedding Comparison
III.2.2. Electromagnetic Simulation
III.3. Modeling of passive elements
III.3.1. Inductance
III.3.1.a. Analytical
III.3.1.b. Model extraction from measurement
III.3.2. Coplanar Lines
III.3.2.a. Analytical model
III.3.2.b. Model extraction from measurement
III.4. Summary
III.5. Bibliography
III.6. Appendixes:
A. Zc, = and εr eff calculation from S parameters measurement
B. Conformal mapping
C. Discontinuities modeling
Chapter IV – Design of millimeter wave receiver building blocks
IV.1. Dynamic range specification for a receiver
IV.1.1. Noise Figure
IV.1.2. Linearity
IV.1.3. Reception sensitivity and dynamic range
IV.2. Millimeter wave LNA and Mixer state of the art in industrial silicon technologies
IV.3. Millimeter wave LNA Design considerations
IV.3.1. LNA stability
IV.3.1.a. Techniques to achieve stability
IV.3.1.b. Stability in multi-stages amplifiers
IV.3.2. LNA design
IV.3.2.a. Noise Figure for two ports network amplifier
IV.3.2.b. Transistor impedance matching
IV.3.2.c. LNA topologies
IV.3.2.d. Millimeter wave matching network
IV.3.3. LNA design methodology summary
IV.4. Millimeter wave CMOS SOI building blocks
IV.4.1. 80GHz and 94GHz CMOS SOI single stage common source amplifier
IV.4.1.a. 80GHz CMOS SOI single stage amplifier simulations and measurements
IV.4.1.b. 94GHz CMOS SOI single stage amplifier simulations and measurements
IV.4.2. 80GHz CMOS SOI three stages LNA
IV.4.2.a. 80GHz CMOS SOI three stages LNA simulations and measurements
IV.4.3. 60GHz CMOS SOI three stages LNA
IV.4.3.a. 60GHz CMOS SOI three stages LNA simulations
IV.4.4. 60GHz CMOS SOI drain pumped mixer
IV.5. Millimeter wave bulk CMOS 65nm building blocks
IV.5.1. 60GHz 4 stages bulk CMOS LNA with ESD protections
IV.5.1.a. Comparison between measurements and simulations
IV.5.1.b. Performance summary of the 60GHz CMOS LNA for different power consumptions
IV.5.2. 60GHz bulk CMOS resistive mixer
IV.5.3. 60GHz bulk CMOS front-end co-integration
IV.5.4. Comparison between CMOS bulk and SOI for mm-wave applications
IV.5.4.a. Circuits comparison
IV.6. Summary
IV.7. Bibliography
IV.8. Appendix:
Conclusion
