Project Topics
Get Complete Project Material File(s) Now! »
UniVed Multi-Level Design Environment for Mixed Signal Systems
Mixed Signal systems design involves complex models, as it manages a several number of com-ponents. At this level of complexity, circuit-level simulations have to be used in moderation and global validations can only be done at the system level. With the increasing popularity of wireless communication systems, RF circuit design became very important. At those high frequencies and when using submicronic technologies, the design methods based on simpliVed models, cannot be used. Until recently, such complex systems were validated by hardware/FPGA [Pena07].
A conventional design Wow operates a top-down design and a bottom-up veriVcation [Gielen00]. When the performance of a level of abstraction does not match to the speciVcations, a redesign is operated at this level of abstraction, changing the topology or modifying the parameters involved in the degrees of freedom of the design.
A more innovative design Wow, presented in Fig. 2.1, manages a performance/speciVcation im-port/export between the levels of abstraction [Carloni02, Rabaey06]. It permits to beneVt from the lower level informations, allowing precise and fast simulations. In this kind of Wow, reVning system-level models is important to be able to back-annotate the circuit-level performance [Rutenbar07]. Furthermore, a platform-based methodology has been presented in [Ferrari99, Sangiovanni-Vincentelli04], replacing the traditionally called top-down and bottom-up designs by a meet-in-the-middle Wow. The illustrated design examples for a platform-based design always processed the performance evaluation by simulation [Carloni02, Nuzzo05]. The platform-based design is an in-teresting approach but rarely applied to a complex system as it supposes to have a collection of architectures or topologies for each component.
In our work, we followed the multi-level design Wow, presented in Fig. 2.1, exchanging the re-sults of system-level simulations: « the speciVcations », and the results of circuit-level performance evaluation: « the performance ». Optimizing this Wow implied making choices for each level of ab-straction. These choices are discussed, in the state of the art of mixed-signal design and simulation tools in Section 2.3.
As the Vrst stage of a complete multi-level design Wow, the system-level modeling state of the art is presented in this section. For the past 20 years, hardware description languages have been widely used to model and simulate systems belonging to various engineering Velds, from digital and analog electronics to mechanics, RF and even battery cell chemistry. The system-level description has been classiVed into levels of abstraction [Vachoux97]: functional level for signal Wow diagrams described by mathematical equations and behavioral level for block diagrams described by DAE (DiUerential-Algebraic Equations) or s-domain transfer functions. Electronic Design Automation (EDA) indus-try recently proposed coherent modeling and simulation frameworks that allow the description of systems from diUerent disciplines and for the description of interactions between these systems. These frameworks use VHDL-AMS [Christen99, Ashenden02, Normark04, Pecheux05] and Verilog-AMS [Frey00,Pecheux05] as eUective backbones for modeling the behavioral level. However, when dealing with Mixed Signal systems, like a Wireless Sensor Networks (WSN) containing dozens of nodes, and with a carrier frequency of a few gigahertz, these frameworks rapidly show their limita-tions in terms of simulation speed. Up to now, the only way to validate the communication between WSN nodes was to run test benches with hardware component [Pena07].
Recently, SystemC AMS [sysb, Vachoux04], an AMS extension to the widely used SystemC, has been proposed for eXcient high-level modeling and simulation of Mixed Signal systems. As illustrated in Fig. 2.2, the idea behind SystemC AMS is to Vll a missing « architectural » level of abstraction in Mixed Signal systems. The language has the advantage of being a simple C++ library, and therefore to inherit the experience of 30 years of contribution and optimization. In Fig. 2.3, [Mahne11] presented the levels of abstraction covered by the mostly used languages in SoC design. The segment representing SystemC AMS language begins in a very high level of abstraction as it is based on C++, and covers additional levels as the language implements a complete library for system-level simulation.
When our work started, the state of the art around SystemC AMS was limited to some simple implementations [sysc]. Some applications were presented using SystemC AMS, for example, mod-
eling acceleration sensor arrays [Markert06] or for modeling a wired communication system [Ein-wich05]. Fairly complex systems were developed in these case studies but they lacked reVned mod-els for the analog blocks taking into account circuit non-idealities.
ReVned Behavioral Modeling of Analog and RF Components
In the state of the art section, we pointed a lack of complex systems model that implemented non-idealities. ReVned models, taking into account circuit non-idealities of the analog and RF blocks are also presented in this work (Chapter 4), with a special care for genericity of models. Thus, the imple-mented SystemC AMS model reVnement consists of three kind of block: the analog component, the RF component and the sine wave source component. An other paper [Vasilevski08b, Vasilevski08a] presented this extended work with model reVnement and simulation improvement.
Analog and RF Circuit Analysis and Performance Evaluation
We implemented a performance evaluation procedure that is motivated by two main points il-lustrated in Fig. 2.6: back-annotation of system-level reVned models and circuit-level optimized biasing and circuit sizing. Each analyzed topology is associated to a symbolical admittance ma- trix built from the complete small-signal model of the circuit. This way the linear performance matches perfectly with a transistor-level simulation result. The performance evaluation procedure also supports nonlinearity thanks to the use of Volterra series and an accurate implementation is incorporated into the procedure. To maintain the homogeneity of the Wow the matrices of perfor-mance are produced in a C++ format.
Systematic Circuit-Level Design and Optimization of Analog and RF Circuits
We have chosen an equation-based methodology following Fig. 2.7, but we considered that the control on the precision is too much dependent on the speciVcations and the technology. By experi-ence, the approximation that is validated for one conVguration could be invalid for another. That’s why, the eUort was done on describing precisely the performance to make it as generic as possi-ble the synthesis procedure. Furthermore, comparing to a simulation-based methodology, the speed of our approach is better as we avoided heterogeneous round trips between diUerent softwares, as the entire environment is C++ based, and since we avoided transient simulation for nonlinear performance evaluation.
As described in Fig. 2.7, additionally to the previously described performance evaluation pro-cedure, transistor-level circuit biasing/sizing and optimization procedures have been implemented to complete the equation-based circuit design Wow. C++ based CAIRO+ and CHAMS have been used for precise sizing and small-signal parameters extraction. The performance is calculated nu-merically to allow a complex circuit to be analyzed very fast. Thus, the contribution in this Veld consisted of implementing a circuit-level equation-based methodology that provides a high speed of execution thanks to a uniVed C++ implementation.
The methodology has been applied to two diUerent design examples: a GmC integrator for a ADC design and a RF Low Noise AmpliVer for a ZigBee RF receiver design. The examples have been chosen as they are both mixed-signal components that constitute a Wireless Sensor Network Node.
UniVed Multi-Level Design Environment for Mixed Signal Systems
Our approach is inspired by the idea of building a communication between the abstraction levels as described in Fig. 2.1. We propose a multi-level design Wow and we apply this approach to a Wireless Sensor Network (WSN) node design. By incorporating the circuit-level evaluated performance into the system-level models, we are able to run fast but also accurate simulations. The systematic de-sign Wow is entirely implemented in a uniVed C++ environment thanks to the use of C++ libraries for each stage: SystemC AMS, CHAMS, GiNaC. By describing the entire Wow in a C++ environ-ment, the design procedures are packaged in a generic analog IP. To demonstrate the methodology, two case studies are presented, the continuous-time ADC and the Zigbee RF transceiver they constitute the mixed-signal components of the Wireless Sensor Network node.
Modeling using Timed Data Flow Model of Computation
In our application, the multi-rate TDF MoC is of particular interest, whereby continuous-time be-havior of a subpart of an analog block is embedded into a data Wow module processing method. As this MoC runs discrete-time non-conservative simulations, the behavior is expressed by the transient Wow of samples. One sample is described by a value and associated to an absolute time. Modeling in SystemC AMS TDF is describing the behavior that produces each sample and manag-ing the simulation settings. Understanding both concepts is important to get a good idea of what can be modeled and how is it modeled.
At Vrst, let’s describe the behavior of a SystemC AMS simulation. The designer has the freedom of the complexity and the granularity of the behavior, and he can beneVt from the ability of mixed-signal systems description. The complexity because all the standard C++ functions are available, acquiring the experience of more than 30 years. Moreover, external C++ libraries can be included, allowing the use of shared experience, for example using a FFT computation. The granularity be-cause of the ability of hierarchical description that allows the control of the level of details of a component, as illustrated in Fig. 3.3. A higher level of details allows to follow the intermediate sig- nals, to analyze the eUect of non-ideal components to the global behavior. The TDF components are called modules and the list of interconnected TDF modules is called a cluster. The cluster simulation plan is elaborated by a static scheduler thanks to the simulation settings. Finally, about the ability of mixed-signal systems description, the designer can easily connect TDF modules to Discrete Event (DE) SystemC digital modules. Actually, SystemC AMS is capable of time signal conversion be-tween a constant step as in SystemC AMS TDF MoC and variable step as the SystemC DE MoC. This makes possible complex simulations with digital and analog components involving complete description of a microcontroller like the Wireless Sensor Network node that will be presented in Section 3.3.
Secondly, about managing the simulation settings, actually, they are all user-deVned. In one hand, the designer has to verify the coherence of the simulation settings. It is a hard work of balancing between precision and simulation speed. It implies that the designer knows exactly the frequency of the application at each stage. In an other hand, the designer is supposed to understand Simulation timestep each stage of his own application. By managing himself the simulation settings, all is in control, the designer can use the knowledge to increase the speed of simulation.
There are three main simulation settings in SystemC AMS TDF: simulation timestep, simulation rate, sample delay. Each sample is generated in a constant user-deVned time distance called simu-lation timestep as depicted in Fig. 3.4. In case of a behavior that describes both low-frequency and high-frequency signals in diUerent subparts, a simulation rate can be attached to the input or output of the blocks to increase or decrease the samples data rate. The rate value set at input of a module corresponds to the number of available samples that can be read in one process activation. The rate value set at output of a module corresponds to the number of necessary samples that have to be written in one process activation. As presented in Fig. 3.5, a rate of 1 at the input of module B im-plies that in one process activation, one sample is available to be read from module B input. A rate of 3 at the output of module B implies that 3 samples have to be written in one process activation. Finally, rate 1 at input of module C implies that 1 sample is available at each process activation. This way, when 2 activations are processed in modules A and B, 6 activations are processed in module C. The process activations are automatically and statically scheduled during the elabora-tion procedure, before the simulation starts. For the example Fig. 3.5, the static scheduler can build an activation sequence « ABCCC ». The designer needs to set one simulation timestep per clusters (in a chosen module deVnition) and to maintain the coherence between the simulated signal and the applied sampling at each module thanks to the simulation rate setting. With those informations, the scheduler will be able to propagate the timestep setting to all the connected modules of the cluster. A last user-deVned simulation setting is delay. It can be related to the chosen behavior but also to a A modeling constraint. As depicted in Fig. 3.6, a feedback loop needs to be delayed to make possible the static scheduling.
Appendix A presents TDF Model of Computation through the example of modeling an RF trans-mitter with its testbench. It illustrates practically the essential concepts of SystemC AMS TDF modeling and introduces the language syntax.
Wireless Sensor Network Node Model
As an example of mixed-signal systems modeling, we have chosen a Wireless Sensor Network (WSN) node. This section describes the ideal implementation of the WSN components that was used to run a Vrst validation process.
A wireless sensor network is a network of autonomous devices that uses sensors to monitor environmental conditions such as temperature, sound, motion and contaminants at distributed ge-ographical locations. As shown in Fig. 3.7, a typical node contains an ADC for analog to digital conversion, a microcontroller executing the embedded application (data processing) and the RF transceiver for wireless communication.
The behavior of the implemented WSN node consists of simply propagating acquired data to RF communication device. The ADC which will be detailed in Section 3.3.1 converts analog measures read from the input to 8-bit digital values. An ATMEGA128 [atm] microcontroller, presented in Section 3.3.2, reads the 8-bit value from an input port and executes instructions to serialize the read data. The serial bitstream is sent from a 1 bit port of the microcontroller to the RF transceiver, Section 3.3.3. The signal is Vnally sent using a QPSK modulation, this is the RF output of the node.
The following Sections 3.3.1 to 3.3.3 present the details of the chosen architecture and the Sys-temC AMS implementation. The implementation is described with listing examples to point the behavior description and with block schematics to visualize the hierarchy and the simulation set-tings of the whole component.
Table of contents :
Introduction
1.1 Outline
2 Motivation and State of the Art
2.1 Introduction
2.2 UniVed Multi-Level Design Environment for Mixed Signal Systems
2.3 State of the art of Mixed-Signal Design and Simulation tools
2.3.1 Mixed Signal Systems Modeling and simulation
2.3.2 Systematic Circuit Analysis and Design
2.4 Major Contributions
2.4.1 Mixed Signal Systems Modeling with SystemC AMS
2.4.2 ReVned Behavioral Modeling of Analog and RF Components
2.4.3 Analog and RF Circuit Analysis and Performance Evaluation
2.4.4 Systematic Circuit-Level Design and Optimization of Analog and RF Circuits .
2.4.5 UniVed Multi-Level Design Environment for Mixed Signal Systems
2.5 Conclusion
3 Mixed Signal Systems Modeling with SystemC AMS
3.1 Introduction
3.2 SystemC AMS
3.2.1 Models of Computation
3.2.2 Modeling using Timed Data Flow Model of Computation
3.3 Wireless Sensor Network Node Model
3.3.1 ADC Model
3.3.2 Microcontroller Model
3.3.3 RF Transceiver Model
3.3.4 Simulation Results
3.4 Baseband Equivalent Modeling for Fast RF simulation
3.4.1 Baseband Equivalent Technique
3.4.2 SystemC AMS Implementation
3.5 Conclusion
4 ReVned Behavioral Modeling of Analog and RF Components
4.1 Introduction
4.2 Model ReVnement of Analog Components
4.2.1 Gain
4.2.2 Noise
4.2.3 Implementation
4.2.4 Results
4.3 Model ReVnement of RF Components
4.3.1 Gain
4.3.2 Noise
4.3.3 Nonlinearity
4.3.4 Implementation
4.3.5 Results
4.4 Model ReVnement of Sine Wave Source Component
4.4.1 Non-idealities
4.4.2 Implementation
4.4.3 Results
4.5 Conclusion
5 Analog and RF Circuit Analysis and Performance Evaluation
5.1 Introduction
5.2 Motivation
5.3 ModiVed Nodal Analysis
5.3.1 The MNA library based on Maxima
5.3.2 Task Scheduling for a Systematic Circuit Analysis and Performance Evaluation
5.4 Linear Performance Evaluation
5.4.1 Voltage Gain
5.4.2 Input Impedance
5.4.3 Output Noise
5.5 Nonlinear Performance Evaluation
5.5.1 Nonlinearity modeling in analog integrated circuits
5.5.2 Volterra kernels
5.5.3 Direct Performance Calculation
5.5.4 Systematic Nonlinear Performance Evaluation
5.6 Conclusion
6 Systematic Circuit-Level Design and Optimization of Analog and RF Circuits
6.1 Introduction
6.2 Proposed Circuit-Level Design Flow
6.2.1 Transistor and Passive Elements Biasing/Sizing
6.2.2 Performance Evaluation
6.2.3 Optimization Procedure
6.3 Case Study I: GmC Integrator
6.3.1 DC Biasing
6.3.2 Transistor and Passive Elements Sizing
6.3.3 Performance Evaluation
6.3.4 Optimization Procedure
6.3.5 Design Examples
6.4 Case Study II: Low Noise AmpliVer
6.4.1 DC Biasing
6.4.2 Transistor and Passive Elements Sizing
6.4.3 Performance Evaluation
6.4.4 Optimization Procedure
6.4.5 Design examples
6.5 Conclusion
7 UniVed Multi-Level Design Environment for Mixed Signal Systems
7.1 Introduction
7.2 The UniVed Multi-Level Design Flow
7.3 Case Study I: GmC Integrator Design for Sigma-Delta ADC
7.3.1 Design Flow
7.3.2 Results
7.4 Case Study II: Low Noise AmpliVer Design for ZigBee RF Transceiver
7.4.1 Design Flow
7.4.2 ZigBee RF Receiver Architecture And Implementation
7.4.3 Results
7.5 Conclusion
8 Conclusion and Future Work
8.1 Conclusion
8.2 Future Work
9 List of Publications
A SystemC AMS: Timed Data Flow Modeling
A.1 Modeling using Timed Data Flow Model of Computation
A.1.1 AmpliVer Model
A.1.2 1-bit DAC Model
A.1.3 Rate Transition
A.1.4 Modulator Model
A.2 Hierarchical Modeling
A.2.1 Transmitter Model
A.3 The Testbench.
A.3.1 Digital Pulse Source Model
A.3.2 The Main Function
B ModiVed Nodal Analysis library for Maxima language
References
