Wireless Sensor Network Attacks: An Overview and Critical Analysis 

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Chapter 4 Effect of Jamming attack on the chip Synchronization in DSSS

Introduction

The probability of bit error of chaotic-DSSS system has been investigated in the previous chapter under the condition of perfect chip synchronization. However, the performance of chaotic-DSSS system highly depends on the chip synchronization [56]. This chapter analyzes the synchronization performance under the Gaussian and repeater jammers.
The chip synchronization is crucial for DSSS-CDMA. In this system, each bit is spread with a chip sequence. The chip sequences are generated both in the transmitter and receiver. The chips on the receiver side have to be synchronized with the transmitted chip sequences. The synchronization performance in the presence of channel noise and fading has been ana-lyzed in [56–63], and new methods for enhancing the chip synchronization performance has been suggested in [64–67]. To achieve the chip synchronization, [68] used the chaotic pilot signal. [68] also investigates the performance of the chip synchronization under Gaussian noise. The usage of the pilot signal for the synchronization is explained later in this chapter. In addition, [56] has introduced a burst mode chip synchronization for the Minimum shift keying (MSK) Receiver and has implemented it on WNS which uses IEEE 802.15.4. How-ever, the performance analysis of synchronization in Chaotic-DSSS system under jamming attack has not received considerable attention from researchers.
The performance of chaotic-DSSS system is critically dependent on the chip synchro-nization. Therefore, this chapter investigates the synchronization performance of such sys-tems under Gaussian and repeater jammers. The analyses are based on the effects of these jammers on the probability of detection and the probability of false alarm. The theoretical results are validated using MATLAB simulations. The content of this chapter has been published as a journal paper in [69].

System description

Chaotic sequences

The DSSS-CDMA system in this study uses chaotic sequences to present a bit. These sequences have to be orthogonal so that multiple users can share the same channel. Each member of a sequence is called a chip. There are different chaotic maps to generate these chips, e.g. Logistic map, Cubic map, Skew tent map, Henon map, and Bernoulli-shift map Authors in [71] show that communication performance slightly changes based on the applied chaotic map. In this study, for consistency with our previous chapter, the Logistic map is used. Note that our analyses and the mathematical developments are applicable for the different chaotic maps. The Logistic map has the following function:
The mean value of these sequences equals 0.5. To make a comparison with the conventional binary sequences, we multiply them by 2. Besides chaotic sequences, there are a large number of sequences that are used in a DSSS-CDMA system, e.g, pseudo-random m-sequences and Gold sequences. However, due to their pseudo-random nature and limited number, they are prone to interception. On the other hand, the number of orthogonal chaotic sequences is random-like and very large, theoretically infinite depending on initial condi-tions. Therefore, having these properties, the chaotic sequences are adding an extra level of security against eavesdroppers [72]. Moreover, the mathematical development in this study is applicable to different chip sequences including all standard binary sequences.
The normalized autocorrelation of a chaotic signal is presented in the Fig. 4.1. The autocorrelation of a chaotic sequence behaves like an impulse signal; it has its maximum when τ equals zero and is zero elsewhere.

DSSS-CDMA system block schematic

Based on the nature of DSSS-CDMA system, b1j is spread by sequence of chips c1i ( b1j is the jth bit of the message which is sent by the first user). It is then passed through a modulation and interleaver block. The effect of modulation and interleaver have been studied in [73].
For synchronization, a pilot signal is also added and sent along with the message signal which its parameters are denoted by b0 and c0.
The noise and jammer are introduced to the signal in the channel and also the effects of delay in the signal is considered. We followed the standard procedure of communication systems analysis, neglecting the influence of the distance and using the concept of white Gaussian noise to characterize the channel. We did not consider the effect of fading in this study even though the effect of fading in the synchronization is well investigated in [57, 59]. Our mathematical development can be extended to the fading channels.
On the receiver side, the signal is demodulated and passed through the deinterleaver. Next, it is multiplied by the chip sequences which are generated locally by the sequence synchronization block. Then, it is entered to the correlator. Finally, the decision making circuit constructs b1j .
In this chapter, the effect of repeater jammer is considered in discrete time. Therefore, same as previous chapter, each chip is sampled M times.

Jammers

In this study, two types of jammers, i.e. Gaussian and repeater jammers, are considered to analyze the performance of the synchronization block.

Gaussian jammer

The Gaussian jammer makes Gaussian noise to jam the system. This type of jammer has the same properties as the jammer which is used in the previous chapter. In this study, the Gaussian jammer is compared with the repeater jammer.

Repeater jammer

The repeater jammer [74–76] attacks the communication link by repeating the transmitted signal. The block diagram of the repeater jammer is presented in the Fig. 4.2. The repeater jammer receives the transmitted signal with the delay of Td . This delay occurs because of the physical distance between the transmitter, receiver and the jammer. Also, Jammer amplifies the received signal by a.

Synchronization

The importance of synchronization in DSSS-CDMA

To find the importance of the synchronization in the DSSS-CDMA system, we show the effect of delay on the probability of bit error. The output of the correlator in the case of delay is given by:
where, τ represents the delay in the system and 2β is the number of chips per bit. Also, Ec, EN and E j are the power of chip, noise and jammer, respectively. Note that in Fig. 4.2, is equal to E j/Ec.
Here, w is a function of a large number of random variables. These variables are in-dependent and identically distributed (i.i.d.). Therefore, according to central limit theorem (CLT), w has a Gaussian distribution. Thus, the probability of bit error is equal to:
2 ·var [w]
When the system is not synchronized (in the presence of delay), the mean value of (4.2)
is equal to:
By substituting (4.4) in (4.3), the probability of bit error becomes:
Thus, the delay between the received signal and the locally generated sequences has a sig-nificant effect on the probability of bit error. In the following section, the synchronization process in DSSS-CDMA system is explained.

Schematic of synchronization block

In DSSS-CDMA system, the synchronization happens in two phases: acquisition and track-ing [77].
In the acquisition phase, the delay is removed with the resolution of a chip duration (Tc). Then, during the tracking phase, a fine tuning is done to eliminate the delay within a chip duration. In this chapter, we assume that the delay is a multiple of Tc. Therefore, only the acquisition phase is investigated.
As mentioned earlier, the synchronization is crucial for DSSS-CDMA system. To per-form the synchronization, a pilot signal is sent with the message signal. The bits in the pilot signal have a value which is equal to +1.
The block diagram of the acquisition section is illustrated in the Fig. 4.3. In the ac-quisition section, the received signal is demodulated. Then, it is multiplied by the locally generated signal and enters the correlator.
In the next step, the outcome of the correlator is passed through the square law device. Similar to the autocorrelation function, the square law device reaches maximum when τ is equal to zero. In other words, the synchronization signal and locally generated chips are aligned. Therefore, a threshold value (ZT ) is set such that if the outcome of the square law device becomes greater than ZT , the synchronization becomes successful. Otherwise, the locally generated chips are shifted for one chip, and the process is repeated until the outcome of the square law device becomes greater than ZT . Here, the probability of detection is defined as a probability in which the delay does not occur between the pilot signal and locally generated chips and the correlator outcome becomes greater that ZT . On the other hand, the probability of false alarm is defined as the case in which the correlator outcomes are higher than ZT , but there is a delay between the pilot signal and locally generated chips.
Mathematical model
Our performance analysis of the acquisition section is based on two key factors of the syn-chronization block: the probability of detection and the probability of false alarm.
In this section, the performance of DSSS-CDMA synchronization is modeled mathemat-ically. We begin with modeling of the distribution of the correlator outcome for Gaussian and repeater jammers. Then, we calculate the probability of detection and the probability of bit error based on the outcome of the correlator distribution.

The correlator outcome for a Gaussian jammer

In this section, two hypotheses have been defined based on the occurrence of delay between locally generated and pilot chips: 1) Misalignment: when a delay occurs between locally generated and pilot chips, 2) Alignment: when no delay occurs.
The distribution of the correlator is calculated for both hypotheses (misalignment and alignment).
The correlator outcome for a Gaussian jammer in the case of misalignment
The correlator outcome, in the case of misalignment, can be expressed as:
A+B+C
where M is the number of sampled chips per bit and τ is the delay. n and J represent the noise and Gaussian jammer signal, respectively.
Considering the orthogonality of chaotic sequences, the mean value of (4.6) is given by:
[Uunsyn] = E[A + B +C] = 0
Also, same as the previous chapter, the variance of Usyn is obtained from:
σU2unsyn = VAR(A) + VAR(B) + VAR(C) Therefore,
The correlator outcome for a repeater jammer
The same procedure for calculating the outcome of the correlator for the Gaussian jammer is applied here. As mentioned earlier, there is a delay between the transmitted signal and the repeater jammer (Td ). Based on this delay, two kinds of repeater jammers can be defined: slow and fast repeater. When the delay between message signal and repeater jammer is greater than Tc, the repeater is considered as a slow repeater, and when the delay is less than Tc, the repeater is considered as a fast repeater.
The correlator outcome for a slow repeater The correlator outcome can be defined as
For simplifying the mathematical expressions, we assume that the channel between the repeater jammer and the transmitter is noise free. Further,
Rim =     Ec.√2c0im
To make a comparison between repeater and Gaussian jammer, it is divided by fore, (4.18) can be redefined as:
A +B −C
√There-
Also the variance of (4.20) is given by:
Therefore, the outcome of correlator’s distribution when the delay between the repeater and the message is greater than Tc is given by
Further, in the case of alignment:
F+G+H
The outcome of correlator can be expressed as:
√Usyn ≈ G 2β                                               Ec , β Ec + β EN + β E j
The correlator outcome for a fast repeater
The outcome of the correlator under the fast repeater jammer, in the case of misalignment, is expressed as:
where TD is smaller than TC; Therefore, (4.26) can be rewritten as:
A′′ +B′′ +C′′ −D′′
Where k is the number of sampled chips in the jamming sequence which overlaps with the message sequence. Also, the overlapping factor (ϑ) is defined as the ratio of k to the number of samples per chip (M).
The mean value of (4.27) is given by;

Table of Contents
Table of Contents 
List of figures 
List of tables 
List of abbreviations 
1 Introduction 
1.1 History of secure communication
1.2 Security of WSN
1.3 Objectives and Contribution of the Thesis
1.4 Thesis outline
2 Wireless Sensor Network Attacks: An Overview and Critical Analysis 
2.1 Introduction
2.2 Denial of Service Attacks
2.3 Privacy Attacks
2.4 Impersonation Attacks
2.5 WSN attack analysis
2.6 Conclusion
3 Analysis of Chaos-DSSS under Jamming Attack 
3.1 Introduction
3.2 System block schematic and assumptions
3.3 System performance
3.4 Result analysis and discussion
3.5 Conclusion
4 Effect of Jamming attack on the chip Synchronization in DSSS 
4.1 Introduction
4.2 System description
4.3 Synchronization
4.4 Mathematical model
4.5 Result and Discussion
4.6 Conclusion
5 Syncim: A new impersonation attack against chip synchronization in WSN 57
5.1 Introduction
5.2 Syncim attack description
5.3 Mathematical modeling of the Syncim attack
5.4 Discussion
5.5 Conclusion
6 A New Approach for Bit Error Rate Analysis ofWide-band DSSS-CDMA System with Imperfect Synchronization under Jamming Attacks 
6.1 Introduction
6.2 System description
6.3 Mathematical development of scenario 1 and 4
6.4 Mathematical development of scenario 2 and 3
6.5 Result and discussion
6.6 Conclusions
7 Secrecy Enhancement of Fix Chaotic-DSSS in WSNs 
7.1 Introduction
7.2 System description and assumptions
7.3 Interception vulnerability of fix chaotic DSSS
7.4 Enhancing the security of fix chaotic-DSSS using fake users method
7.5 Conclusion
8 Conclusions and future works 
8.1 Conclusions
8.2 Future Works
References
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Physical Layer Security in Wireless Sensor Networks

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