Cell consumption during the channel hot electron programming operation

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Flash memory architectures

Flash memories are organized in arrays of rows (word lines or WL) and columns (bit lines or BL). The type of connection determines the array architecture (figure 1.7).
NOR: The NOR architecture was introduced for the first time by Intel in 1988. The cells are connected in parallel and in particular, the gates are connected together through the wordline, while the drain is shared along the bitline. The fact that the drain of each cell can be selectively selected enables a random access of any cell in the array. Programming is generally done by channel hot electron (CHE) and erasing by Fowler-Nordheim (FN). NOR architectures provide fast reading and relatively slow programming mechanisms. The presence of a drain contact for each cell limits the scaling to 6F2, where F is the smallest lithographic feature. Fast read, good reliability and relatively fast write mechanism make NOR architecture the most suitable technology for the embedded applications requiring the storage of codes and parameters and more generally for execution-in-place. The memory cells studied in this thesis will be integrated in a NOR architecture for embedded applications.
NAND: Toshiba presented the NAND architecture development in 1987 in order to realize ultra high density EPROM and Flash EEPROM [Masuoka ’87]. This architecture was introduced in 1989 and presented all the cells in series where the gates were connected by a wordline while the drain and the source terminals were not contacted. The absence of contacts means that the cell cannot be selectively addressed and the programming can be done only by Fowler-Nordheim. On the other hand, it is possible to reach an optimal cell size of 4F2, thus a 30% higher density than in NOR cells. In NAND architecture programming is relatively fast but the reading process is quite slow as the reading of one cell is done by forcing the cell in the same bit line to the ON state. The high density and the slow reading but fast writing speeds make NAND architecture suitable for USB keys, storing digital photos, MP3 audio, GPS and many other multimedia applications.

Silicon nanocrystal memory: state of the art

The market of nonvolatile Flash memories, for portable systems, requires lower and lower energy and higher reliability solutions. The silicon nanocrystal Flash memory cell appears as one promising candidate for embedded applications. The functioning principle of discrete charge trapping silicon nanocrystal memories (Si-nc) is similar to floating gate devices. In this thesis we consider the integration of Si-nc memories in NOR architecture for embedded applications programmed by channel hot electron and erased by Fowler-Nordheim mechanisms.
There are many are the advantages to using this technology:
– Robustness against SILC and RILC (Radiation Induced Leakage Current), this enables to scale the tunnel oxide thickness to be scaled down to 5nm, while the ten year data retention constraint is guaranteed. Moreover the operation voltages can be decreased too [Compagnoni ’03] [Monzio Compagnoni ’04]. Further improvements can be achieved using cells with a high number of nanocrystals [De Salvo ’03].
– Full compatibility with standard CMOS fabrication process encouraging industrial manufacturability, reducing the number of masks with respect to the fabrication of floating gate device [Muralidhar ’03] [Baron ’04] and ease of integration [Jacob ’08].
– Decrease in cell disturb, due to the discrete nature of nanocrystals and their smaller size than a floating gate, the coupling factor between the gate and drain is reduced as well as the disturbs between neighboring cells.
– Multi level applications, the threshold voltage of a silicon nanocrystal transistor depends on the position of stored charge along the channel [Crupi ’03] [De Salvo ’03]. Despite these peculiarities two main drawbacks characterize the Si-nc memories:
– The weak coupling factor between the control gate and nanocrystals. This implies finding a method to keep the program/erase voltages small and to take advantage of the decrease in tunnel oxide thickness [De Salvo ’01].
– The spread in the surface fraction covered with Si-nc limiting this type of cell for high integration density applications [Gerardi ’04].
IBM presented the first Si-nc memory at IEDM [Tiwari ’95] in order to improve the DRAM (Dynamic Random Access Memory) performance using a device with characteristics similar to EEPROM. The polysilicon floating gate is replaced by silicon nanocrystals grown on tunnel oxide by Low Pressure Chemical Vapor Deposition (LPCVD) two step process. This type of fabrication enables the size and density of nanocrystals to be controlled separately [Mazen ’03] [Mazen ’04].


Flash technology for embedded applications

The 1T silicon nanocrystal technology is not the only solution to replace the Flash floating gate. In particular for the market of embedded applications the Flash memory array is integrated in the microcontroller products with SRAM, ROM and logic circuits achieving System on a Chip solution (SoC). This type of integrated circuit enables the fabrication costs reduction due to the compatibility with the CMOS process, by improving the system performance because the code can be executed directly from the embedded Flash. The most important applications for embedded products are the smart card and automotive, where low energy consumption, fast access time and high reliability are required (figure 1.34). In this scenario each one of main industrial actors searches the best compromise between cell area, performance and cost. In figure 1.35 we show the mainstream Flash concepts proposed by the top players of SoC manufacturers [Strenz ’11].

Table of contents :

General introduction
Chapter 1 – Flash memories: an overview
1.1 Introduction
1.2 The industry of semiconductor memories
1.2.1 The market of non-volatile memories
1.2.2 Memory classification
1.2.3 Flash memory architectures
1.3 Floating gate cell
1.3.1 Basic structure: capacitive model
1.3.2 Programming mechanisms
1.3.3 Erase mechanisms
1.3.4 Evolution and limits of Flash memories Device scaling
1.3.5 Alternative solutions Tunnel dielectric Interpoly material Control Gate Trapping layer
1.4 Silicon nanocrystal memory: state of the art
1.5 Flash technology for embedded applications
1.6 Innovative solutions for non volatile memory
1.6.1 Ferroelectric Random Access Memory (FeRAM)
1.6.2 Magnetic Random Access Memory (MRAM)
1.6.3 Resistive Random Access Memory (RRAM)
1.6.4 Phase Change Random Access Memory (PCRAM)
1.7 Conclusion
Chapter 2 – Electrical characterization of silicon nanocrystal memories
2.1 Introduction
2.2 Experimental details
2.2.1 Experimental setup
2.2.2 Methods of characterization
2.3 Impact of technological parameters
2.3.1 Effect of silicon nanocrystal size
2.3.2 Effect of silicon nitride capping layer
2.3.3 Effect of channel doping dose
2.3.4 Effect of tunnel oxide thickness variation
2.4 Programming window cell optimization
2.5 Benchmarking with Flash floating gate
Chapter 3 – Reliability of silicon nanocrystal memory cell
3.1 Introduction
3.2 Data retention: impact of technological parameters
3.2.1 Effect of silicon nitride capping layer
3.2.2 Effect of channel doping dose
3.2.3 Effect of tunnel oxide thickness
3.3 Endurance: impact of technological parameters
3.3.1 Impact of silicon nanocrystal size
3.3.2 Impact of silicon nitride capping layer
3.3.3 Impact of channel doping dose
3.3.4 Impact of tunnel oxide thickness
3.4 Silicon nanocrystal cell optimization
3.4.1 Data retention optimization
3.4.2 Endurance optimization
3.5 Benchmarking with Flash floating gate
Chapter 4 – Cell consumption during the channel hot electron programming operation  
4.1 Introduction
4.2 Methods of Flash floating gate current consumption measurement
4.2.1 Standard current consumption measurement
4.2.2 Indirect current consumption measurement
4.2.3 New method of current consumption measurement
4.3 Floating gate consumption characterization
4.3.1 Cell consumption Impact of programming pulse shape Impact of drain and bulk biases Impact of channel doping dose
4.3.2 Bitline leakage Impact of lightly doped drain implantation energy TCAD simulations of LDD implantation
4.4 Silicon nanocrystal cell consumption characterization
4.4.1 Impact of programming pulse shape TCAD simulations of current consumption Hybrid silicon nanocrystal cell programming scheme optimization
4.4.2 Impact of gate and drain biases
4.4.3 Impact of tunnel oxide thickness
4.5 Optimized cell consumption
4.6 Benchmarking with Flash floating gate
Chapter 5 – Conclusion
5.1 Perspectives
Chapter 6 – Résumé du travail de thèse en français
6.1 Présentation de la thèse
6.2 Le marché des mémoires à semi-conducteur
6.3 Les mémoires à nanocristaux de silicium
6.4 Caractérisation électrique de la cellule mémoire à nanocristaux
6.5 Fiabilité de la cellule à nanocristaux de silicium
6.6 Consommation de la cellule pendant une opération de programmation par injection d’électrons chauds
6.7 Optimisation de la consommation énergétique
6.8 Comparaison des performances avec la cellule Flash à grille flottante
6.9 Conclusion générale


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