HETEROJUNCTION BIPOLAR TRANSISTORS

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CHAPTER 2: LITERATURE REVIEW

INTRODUCTION

The objective in LNA design is to achieve sufficient gain over a required frequency band while maintaining a very low noise figure. This is crucial for the first amplification stage since it dominates the NF of the system as a whole as shown in where F is the noise factor, GA the associated gain and the subscripts indicate successive amplifier stages [1]. The linearity of the amplifier as well as power consumption are also important specifications and thus limitations that the design must contend with. This chapter provides a review of the literature pertaining to low noise amplifier design and achieving these design objectives. The increased availability of silicon-germanium (SiGe) processes has led to the use of SiGe HBT in many high frequency applications. One of the major reasons for the success of the SiGe HBTs in wireless applications is its low noise capability [4] and high speed,which also makes it attractive for low noise amplifier design; thus the use of HBTs is elaborated. Inductors are also important in RF design and the availability of on-chip inductors have allowed for complete integration of RF circuits. However, passive on-chip inductors are costly in terms of chip area and suffer from a low Q-factor and thus various inductor types and optimization techniques are briefly discussed, as well as the possibility of employing active inductors to avoid these shortcomings at the cost of higher noise.The first part of this chapter discusses the noise sources present in transistors, followed by the effect of these sources in HBT amplifier circuits. The characteristics of HBTs making them suitable for low noise design are discussed, as well as important linearity considerations. Various input matching techniques are then presented, including a detailed discussion of the very common use of emitter scaling to adjust the optimal noise resistance for a simultaneous optimal noise and power input match.

NOISE IN AMPLIFIER CIRCUITS

There are five types of well known noise sources present in circuits with active and passive devices. These are [26]: Thermal noise, shot noise, Flicker or 1/f noise, burst noise and avalanche noise. Thermal noise occurs due to the random thermal motion of electrons. For a given circuit component with a resistance R the average thermal noise voltage is given by where k = 13.8E-24 J/K is Boltzmann’s constant, Δf is the amplifier noise bandwidth and T is absolute temperature. Since the standard definition of noise figure is at T = 290 °K [1] this will be the assumed temperature throughout this thesis unless otherwise stated. Since the thermal noise spectrum is frequency independent within the noise bandwidth it contributes to amplifier white noise. The thermal noise voltage or current is minimized for very small or very large values of R respectively. Shot noise is associated with direct current (DC) flow through a p-n junction and is always present in diodes, MOSFETs and bipolar transistors. In a forward biased p-n junction the forward current exists as a result of holes and electrons gaining enough energy to cross the electric field present in the depletion region. Thus the passage of each carrier across the junction is a random event occurring when a specific carrier has sufficient energy and velocity directed toward the junction and the apparent steady forward current is in fact composed of a large number of random independent current pulses [26]. The fluctuations that occur in this current are called shot noise and is usually specified in terms of its mean-square variation about the average value as where q is the electron charge, ID the average forward current and Δf the amplifier noise bandwidth. The spectrum of shot noise is also frequency independent and thus contributes to white noise.Flicker noise and burst noise are both frequency dependent and occur at lower frequencies. Flicker noise is caused mainly by traps associated with contamination and crystal defects which capture and release carriers in a random fashion. The time constants associated with this process give rise to a noise signal with energy concentrated at low frequencies [26].Burst noise is not fully understood but does show some relation to the presence of heavy-metal ion contamination. Since the dependence of the noise spectral density on frequency for flicker noise is 1/f (pink noise) and that of burst noise 1/f 2 (brown noise) above a cut-off frequency, these noise sources are not important in super high frequency (SHF) circuits, with the exception of voltage controlled oscillators where flicker noise can be up-converted as phase noise [4].Avalanche noise occurs in reverse biased p-n junctions where electrons in the depletion region acquire sufficient energy to create electron-hole pairs by colliding with silicon atoms. This creates large noise spikes and generally dominates all other noise sources when present. The noise magnitude is proportional to the DC flow [26]. This source of noise can be minimized by ensuring the reverse bias voltage is small enough to limit the occurrence of avalanche breakdown. In summary, for high frequency amplifier circuits, assuming reverse bias is sufficiently low such that avalanche breakdown becomes negligible, the noise sources to contend with are thermal noise and shot noise.

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SUMMARY
OPSOMMING 
ACKNOWLEDGMENT 
TABLE OF CONTENTS
LIST OF ABBREVIATIONS
CHAPTER 1: INTRODUCTION 
1.1 BACKGROUND TO THE RESEARCH 
1.2 HYPOTHESIS AND RESEARCH QUESTIONS 
1.3 JUSTIFICATION FOR THE RESEARCH 
1.4 RESEARCH METHODOLOGY
1.5 DELIMITATIONS OF SCOPE AND KEY ASSUMPTIONS 
1.6 CONTRIBUTION TO THE FIELD 
1.7 PUBLICATIONS LEADING FROM THIS RESEARCH
1.8 OUTLINE OF THE THESIS
CHAPTER 2: LITERATURE REVIEW
2.1 INTRODUCTION 
2.2 NOISE IN AMPLIFIER CIRCUITS 
2.3 NOISE IN HBT AMPLIFIERS
2.3.1 Common-emitter amplifier noise and gain parameters
2.3.2 Low noise capability of HBTs
2.3.3 Design for minimum transistor noise figure
2.4 LINEARITY OF HBT AMPLIFIERS 
2.5 INPUT MATCHING
2.5.1 Traditional input matching techniques
2.5.2 Impedance matching in the super high frequency range
2.5.3 Inductive emitter degeneration
2.5.4 Capacitive shunt-shunt feedback technique
2.5.5 LC-ladder input matching network with emitter degeneration
2.5.6 Wideband matching using shunt-shunt feedback
2.6 PERFORMANCE MEASURE TRADE-OFFS 
2.6.1 Noise figure
2.6.2 Linearity
Electrical, Electronic and Computer Engineering x
2.6.3 Gain
2.7 ON-CHIP PASSIVE INDUCTORS 
2.8 ACTIVE INDUCTORS 
2.9 CONCLUSION
CHAPTER 3: SiGe MONOLITHIC TECHNOLOGIES
3.1 INTRODUCTION 
3.2 HETEROJUNCTION BIPOLAR TRANSISTORS 
3.3 HBT MODELS
3.3.1 VBIC – vertical bipolar inter-company model
3.3.2 HICUM – high current model
3.4 METAL AND INTERCONNECT LAYERS 
3.5 8HP AND 7WL RESISTORS 
3.6 CAPACITORS 
3.7 INDUCTORS AND TRANSMISSION LINES
3.7.1 Inductor and RF-line layout considerations
3.8 BOND PADS 
3.9 CONCLUSION
CHAPTER 4: MATHEMATICAL MODELLING 
4.1 INTRODUCTION 
4.2 INPUT MATCHING
4.2.1 LC-ladder network
4.2.2 Capacitive feedback Miller impedance
4.2.3 Input reflection coefficient
4.2.4 Comparison to the inductively degenerated LC-ladder technique
4.3 GAIN EQUATIONS 
4.3.1 Input matching network gain
4.3.2 First stage gain
4.3.3 Second stage gain and gain flattening
4.3.4 Further gain stages
4.4 LNA DESIGN EQUATIONS 
4.5 INPUT MATCHING MODELLING IMPROVEMENT 
4.6 NOISE FIGURE DERIVATION 
4.6.1 Noise sources
4.6.2 Simplifying the circuit
4.6.3 Noise figure equation derivation
4.7 IMPROVING NOISE FIGURE AND GAIN
4.7.1 Noise figure improvement
4.7.2 Simultaneous gain improvement
4.8 LINEARITY APPROXIMATION 
4.9 PERFORMANCE LIMITS AND TRADE-OFFS
4.9.1 Noise figure vs. bandwidth
4.9.2 Parasitic base-collector capacitance vs. lower corner frequency
4.10 LIMITS OF THE MODEL AND CONFIGURATION
4.11 THEORETICAL RESULTS 
4.12 LNA ELECTRONIC DESIGN AUTOMATION 
4.13 CONCLUSION 
CHAPTER 5: SIMULATION RESULTS
5.1 INTRODUCTION 
5.2 CIRCUIT SCHEMATIC AND SPECIFICATIONS OF THE DESIGN
5.4 8HP DESIGN AT 60 GHZ 
5.5 7WL DESIGN FOR 3-14 GHZ
5.6 CONCLUSION 
CHAPTER 6: LAYOUT AND FABRICATION
6.1 INTRODUCTION 
6.2 CIRCUIT LAYOUTS 
6.3 PHOTOS OF THE FABRICATED CHIP 
6.4 PACKAGING 
6.5 PACKAGE PARASITICS AND ITS EFFECT ON PERFORMANCE
6.6 TEST PCB 
6.7 SHORTCOMINGS OF THE TEST PCB 
6.8 CONCLUSION
CHAPTER 7: EXPERIMENTAL RESULTS
7.1 INTRODUCTION 
7.2 MEASUREMENT EQUIPMENT AND TEST PROCEDURE 
7.3 MEASURED S-PARAMETERS 
7.4 MEASURED NOISE FIGURE 
7.5 MEASURED P1DB COMPRESSION 
7.6 CONCLUSION 
CHAPTER 8: CONCLUSION 
8.1 CRITICAL EVALUATION OF THE WORK 
8.2 SUGGESTIONS FOR FUTURE WORK 
REFERENCES 

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