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The Impact of the Variability in Static Random Access Memory
This chapter rst presents a brief summary on the role of SRAMs in mod-ern System-On-Chips and outlines the basic structures and operations of an SRAM circuit. This is followed by the presentation of multi-dimensional variability space model that is used to reproduce in simulations real-world SRAMs that are strongly impacted by variability during the their manufac-turing. Later, SRAM gure of merits that are used to evaluate stability and performance are discussed. SRAM bitcell characterization techniques and the concept of the minimum operating voltage Vmin are presented after a particular focus on the di erent bitcell failure mechanisms.
Introduction to SRAMs limitations in modern System-On-Chips
The variability impact on digital circuits has been a very popular re-search topic for last 15 years [66{68]. This impact manifests in digital logic circuits in the form of delay and leakage power variability [69]. Consid-ering a signal path passing though multiple gates and each gate having its particular delay, the resulting distribution of the collection of delays is assumed as Gaussian-like [69]. The overall delay reduces as the number of gate in the path increases, since variations along a long path can be averaged out [70]. However, analogue and analogue-like systems like Static Random Access Memory (SRAM) and latch registers are more complex, since they rely for their operation on balanced pairs of transistors. The SRAM circuits are particularly concerned from the variability phenomenon, since they are fabricated with most aggressive design rules for density improvements and the manufacturing yield degrades dramatically due to the increased in-die variability [71]. Therefore unlike digital logic circuits, the SRAM requires additional correction and redundancy circuits to overcome the statistical variability impact [72, 73], which costs more area in the same chip. The impact of variability on SRAM circuits has therefore become an important research topic among the academics and the semiconductor industries. The published works refer to the statistical modeling of the variability impact and its characterization both on simulation and silicon measurements, as well as to the improvement techniques to increase the SRAM immunity to variability.
The highly demanding low-power market requests to deal with very so-phisticated applications and thus expects more performance and higher stor-age capacity from on-chip memories. In modern System on Chip (SoC) ap-plications, SRAMs can be used as cache memories, temporary bu ers and large capacity storage RAMs, therefore occupying a signi cant portion of the chip area [74]. This stems from the fact that 20-40% of all program instructions require memory [75] and SRAM is the only e cient and fast storage system for processor caches for the amount of data required by a processor [76]. This heavy-use of SRAMs makes them the main contributor for the overall power consumption of a given chip [77]. The equation (3.1) presents the sum of static and dynamic power of a given digital circuit, which depends on the leakage current Ileak, the operating voltage Vdd, the activity factor indicating the fraction of the circuit that is switching, the overall equivalent capacitance C and the cycle frequency F.
The equation (3.1) evidences that reducing Vdd will reduces both static and dynamic power. Considering the fact that SRAMs are the main contributor for the overall power consumption in a given chip, reducing the memory operating voltage will lead to a signi cant overall power reduction. [73].
At each new technology node, SRAM bitcell footprint is shrunk follow-ing the Moore’s Law by a factor of two as shown in gure 3.1, allowing for a higher memory density (potentially double). As a consequence, today’s SRAM arrays contain more than a billion transistors, thus their manufactur-ing leads to a very large variability in the worst-case values of the transistor electrical parameters. In addition, the local random variability impact is also ampli ed by the aggressive downscaling of the device sizes. This un-avoidable variability phenomenon stands as the biggest obstacle for further density improvements, as well as the reduction of the memory operating voltage, since the variability impact is magni ed in low-voltage memory operations. Figure 3.2 illustrates the stagnation in the SRAM operating voltage scaling as it is recognized by the International Technology Roadmap for Semiconductors (ITRS).
Figure 3.1: SRAM bitcell scaling trend from 65nm to 32nm techonology node for the performance bitcell (squares) and for dense bitcell (diamonds) showing the 50% area reduction [78].
Figure 3.2: SRAM minimum operating voltage reported in ISSCC and VLSI Conferences between 2004 – 2010 (crosses) and ITRS predictions at 2001 and at 2009 (straight lines) [79].
SRAM Bitcell Architecture and Common Op-erations
The conventional SRAM bitcell architecture is the standard 6-Transistors (6T) SRAM bitcell, which consists of two cross-coupled inverters for the content storage and two access transistors for the communication with the external world, as shown in gure 3.3. The cross-coupling is performed as that the output of the rst inverter is connected to the input of the second inverter and the output of the second inverter is connected to the input of rst inverter, forming a bistable latching circuitry. The latch input and out-put nodes, L and R in gure 3.3, represent the bitcell internal nodes. The state of an internal node is forced by the complementary state of the other al-lowing for the data storage. For an optimal performance, the inverters have to be symmetrical and well-balanced in their behavior. The PMOS-NMOS transistors forming an inverter are named as Pull-Up (PU) and Pull-Down (PD) respectively. The access transistors, also called as Pass-Gate (PG) transistor, are controlled via the World-Line (WL) signal and connect the bitcell internal nodes to the Bit-Lines (BL). BLs are external access points to the bitcell, where the information can be read from or written to the cell. To ensure that the access time from both sides is equal in a given bitcell, the access transistors have to be well matched, representing one of the vulnerable points of SRAM to the statistical variability.
An SRAM array is formed by a matrix of cells and each cell is associ-ated to the storage of one bit, hence the name bitcell comes from. Aside from the bitcells, a SRAM contains a signi cant amount of peripheral cir-cuitry including world line pulse generation, addressing logic, sense ampli-er, pre-charge/line bu er and multiplexer circuitry. A block level of SRAM schematic is shown in gure 3.4.
A write operation (WR) in SRAM consist in forcing the bitcell content to the values set on the BLs. Considering the bitcell illustrated in gure 3.3 which has a low-logic level in the node L and high-logic level in the node R, a successful WR results in the toggle of the internal nodes in order to have high-logic level in L and low-logic level in R. The high-logic level and the low-logic level represents the equivalent voltage level that a internal node needs to be able store « 1 » or « 0 » logic values respectively. The write is performed by rst setting left bit-line (BLL) to high-logic level and discharging the right bit-line (BLR) to 0V. Then the access transistors are turned on via the WL signal providing access to the bitcell internal nodes. The high voltage level in the node R is discharged through the access transistor PG2 and the BLR. When the voltage level of the node R goes below the trip point of inverter formed by PU1 and PD1, the bitcell content toggles; the bitcell stores now a « 1 » in the node L and a « 0 » in the node R.
A read operation (RD) from 6T SRAM is performed as follows: Both bit-lines are pre-charged to high-logic level and then access transistors are turned on enabling the connexion between the bit-lines and the bitcell in-ternal nodes. Considering the same bitcell of gure 3.3, during a RD 0 from the node ’L’, the BLL is discharged through the PG1 and PD1 tran-sistors generating a voltage di erence between BLL and BLR. In case of SRAM arrays which contain sense-ampli ers in the peripheral circuity, the BL voltage di erence is captured by a sense-ampli er and the required volt-age di erence to enable sensing depends on the sense-ampli er design.
Figure 3.3: 6T-SRAM Bitcell schematics: Two cross-coupled inverters (top) for the storage of the data are connected to the external world via two access transistors (pass-gates) which are activated with a word-line signal. The transistor-level schematic (bottom) shows also the pull-up (PMOS), pull-down (NMOS) and pass-gate (NMOS) transistors.
Figure 3.4: A block level of SRAM system. Column and row decoder cir-cuitries are driven by the addressing latch which selects the required bitcells. Data Register and I/O bu fers are used to write to cells and are disabled during read cycles when the sense ampli er outputs the stored data. The clock circuitry and the word line driver which determines the word line pulse width, are not shown.
swing in the read circuitry, which causes a signi cant slowing-down in the read speed. Full-swing read is a popular method for ultra-low-voltage (ULV) SRAMs [80,81], since conventional sense-ampli ers can not operate in ULV. A novel ULV sense-ampli er design has been proposed in the literature to overcome this limitation [82].
Alternate Bitcell Architecture
Aside 6T bitcell architectures, to answer to the low-voltage requirements, new derived bitcell architectures as 8T [83], 10T [80] [84] or 11T [85] have been proposed in the literature. The new architectures mostly o er the separation of the write and the read operations improving the bitcell sta-bility and thus increasing immunity to the statistical variability, which ev-idently allows the downscaling of the operating voltage. Per contra, the increased number of transistors in the bitcell enlarges the bitcell footprint and causes an area penalty. The high density requirements to increase the memory capacity raised the design of smaller (denser) bitcell architectures as 5T [86] and 4T [87]. The smaller bitcell architectures allow evidently a higher integration, but on the other hand, the reduced number of transistor degrades the bitcell stability. Variations in the electrical characteristics of the identically-designed transistors are also ampli ed by aggressive scaling of the device sizes. Therefore small bitcell limits the downscaling of the operating voltage.
This research work is concentrated on the conventional 6T bitcell SRAMs, while a 10T bitcell is used in particular for ulta-low-voltage studies. The Ultra-Low Voltage (ULV) 10T bitcell architecture designed for ultra-wide voltage range (UWVR) applications [80, 81] is presented in gure 3.5. The write and reap operations are separated by the use of dual pass-gates to access bitcell internal nodes. The inner pass-gates, PG1 and PG2, are con-trolled by a second world-line signal WLC, whereas the outer read pass-gates, PG1R and PG2R are controlled by WL signal. During write oper-ation, WCL and WL are asserted to open both the outer and inner pass-gates connecting the bitcell to BLs. The dual pass-gate implementation forms outer internal nodes, Lo and Ro, whose voltage levels are equal to the inner internal nodes, L and R. Footer gate transistors, FG1 and FG2, are connected to the outer internal nodes and their gates are controlled by the opposite inner internal node voltage. Considering a bitcell that stores a ’0’ in the node ’L’, thus both Li and L voltage levels are equal to low-logic level voltage, the read operation is performed as follows: First the BLs are pre-charged to high-logic value as for a conventional 6-T SRAM read, then the outer pass-gates PG1R and PG2R are turned-on via WL signal estab-lishing the connexion between outer internal nodes and BLs. PG1R and the footer gate FG1 then discharges the BLL through Lo, without disrupting L and thus increasing the read stability, since the inner internal nodes are pro-tected from charge sharing as the inner pass-gates PG1 and PG2 controlled by WCL are closed.
A Simple Model for the Bitcell Variability Space
While the downscaling in the transistor sizes allows the designers to achieve considerable density improvements, it dramatically increases the in-die variability of the smallest MOS device used in SRAM bitcells. In the same time, since todays electronics devices feature millions of SRAM bitcells and chips might be manufactured in millions, the resulting large variability of the worst-case electrical parameters values increase the risk to obtain a signi cant amount of cells that are far from their nominal attribute. The overall impact of the in-die and within-die variability leads to memory fail-ures and lowers the overall chip yield. The stability and performance analy-sis of worst-case SRAM cells has thus a very relevant technological impact, because it is so tied to the chip yield.
The real-life bitcells, the ones that are manufactured, can not be seen as identical to the nominal design due to the process variability. Each manu-factured bitcell has its proper transistors with their proper electrical char-acteristics; some are close to, some are very far from the nominal design. In real-life bitcells, the variability impact is emerged in many physical design parameter as the oxide thickness, the width and length of channel, the num-ber of dopants, all a ecting the electrical characteristics of manufactured devices. An ideal modeling of the variability in one transistor requires an accurate modeling of all di erent variability sources. At circuit-level, each transistor in the circuit has to be modeled, which increases signi cantly the complexity and the related computing cost, not just because of the increased number of variation parameter, but also due to the fact that MOS charac-teristics are heavily non-linear. The threshold voltage (Vth) plays a fun-damental role in device electrical characterization and stands as the most signi cant parameter for transistor classi cations. The overall variability impact thus can be modeled, as a rst-order approximation, by variations in the device Vth. This approximation is a common approach which is also used in reliability analysis for modeling transistor aging.
Table of contents :
1 General Introduction
2 Variability in Ultra-Deep-Submicron CMOS
2.1 Introduction to Variability
2.2 Variability Sources in CMOS
2.2.0.1 Systematic Variability
2.2.0.2 Random Variability
2.2.0.3 Time Dependency in Variability
2.3 The Improvement Techniques for Variability and New Device Architectures
2.4 Conclusion
3 The Impact of the Variability in Static Random Access Mem-ory
3.1 Introduction to SRAMs limitations in modern System-On-Chips
3.2 SRAM Bitcell Architecture and Common Operations
3.3 Alternate Bitcell Architecture
3.4 A Simple Model for the Bitcell Variability Space
3.5 SRAM Bitcell Failure Analysis
3.5.1 SRAM Bitcell Static (DC) Analysis
3.5.1.1 Static Noise Margin
3.5.1.2 Write Margin
3.5.2 SRAM Bitcell Dynamic Analysis
3.5.2.1 Read-Ability
3.5.2.2 Write-Ability
3.5.2.3 Multiple-Pulse Analysis and Figure of Merits
3.6 6T-SRAM Bitcell Failure Mechanisms
3.7 The Minimum Operating Voltage Vmin
4 SRAM Bitcell Variability Space Modeling for Vmin Estima-tion
4.1 Bitcell Variability Space Modeling using Monte Carlo SPICE simulations
4.2 SRAM Static Vmin Analysis
4.2.1 6T Bitcells Static Vmin Measurements and SPICE Mod-eling Results
4.2.2 Ultra-Low-Voltage SRAM Static Vmin Measurements and Modeling Results
4.3 Bitcell Variability Space Modeling using Smart Algorithm : Hypersphere Most Probable Failure Point Search Methodology
4.3.1 Bitcell Failure Probability Calculation
4.4 SRAM Dynamic Vmin Analysis
4.4.1 Bitcell Dynamic Fail/Pass SPICE Analysis using Hy-persphere Algorithm
4.4.1.1 Read-Ability Test
4.4.1.2 Write-Ability Test
4.4.1.3 Read-After-Write Test
4.4.2 SRAM Dynamic Failures on Silicon
4.5 Application Example: Hypersphere MPFP Search for Inves-tigations on SNM Yield Loss at High-Voltage in 28nm UTBB FD-SOI SRAM bitcells
4.6 Smart Dynamic Back-Biasing Bitcell Vmin Boost in UTBB FD-SOI
4.7 Conclusion
5 Random Telegraph Signal Noise in 28nm UTBB FD-SOI and the impact on 6T SRAM
5.1 Time-Dependent Random Telegraph Signal Noise Variability
5.2 SPICE-level RTS Noise Modeling in UTBB FD-SOI
5.2.1 RTS Trap Characteristics and Particularity of UTBB FD-SOI
5.2.2 Front- and Back-gate Coupling Aware 2-Dirac Charge Inversion model
5.2.3 RTS-aware 6T SRAM SPICE netlist generation in Matlab
5.3 Measurements and Simulation Results
5.3.1 Hardware Setup
5.3.2 Results
5.4 Conclusion
6 General Conclusion
6.1 Key Contributions
6.2 Future Work
