Stacked nanowire FETs: integration challenges and process optimization.

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TCAD Model: Simulation Parameters and Extraction

Several levels of precision cohabit in microelectronic simulations (Figure 2.1). Advanced simulations target specific phenomena using highly precise approach such as band structure computation. A level of precision lower, the components and the technological processes simulations help predicting the devices performance with simplified algorithms and faster computation times. Finally, the compact modeling are dedicated to circuit evaluations involving a significantly higher number of devices. All of these domains complement each other, not to mention experimental characterization which is essential to build a global comprehension of the physics behind the devices and complex architectures. TCAD Sentaurus SDE tool [Sentaurus 2013] is therefore the most efficient way to set up an exhaustive analysis of FinFET and SNWFET. In the following, the key design rules and devices models that fits projections for the 7 nm node technology are first presented (§2.1.1). Transistor intrinsic delay is then defined in §2.1.2 as this value can be used to compare performances in between the different devices. The definition includes an equivalent capacitance model which is therefore simplified in the third section (§2.1.3).
Main geometric parameters are reported in Figure 2.2 in a cross section along with a table. The prediction has been defined in CEA-LETI and based on internal knowledge and state-of-the-art material and patterning abilities according also to the 10nm-node definition from ITRS 2013, [Lacord 2012 TED]. The contacted polysilicon pitch (CPP) defines the pitch between two neighboring gates and LG is the gate length. The equivalent oxide thickness (EOT) is calculated from the formulae recalled in the inset and considers the presence of a high-k layer – HfO2 for instance – above the chemically oxided inter layer (IL): their thickness and dielectric permittivity are respectively THK, εHK, TIL and εIL. The gate spacers are Lspa12 large and isolate the gate over its entire height Tgate. The raised source and drain (RSD) thickness is Tepi and the width and height of the contact above are respectively Lcont and Tcont. Finally, a hard mask (HM) isolating the gate from the source and drain contacts which thickness is TM0.
Figure 2.4 represents a SNWFET featuring three stacks of NWs with a specific “mixed” configuration with one gate-all-around (GAA) suspended NW on top of a trigate NW laying on the buried oxide (BOX). The number of parallel stacks is tunable as well as the number of NW in each stack. The gate configuration can be either fully composed of GAA or alternatively composed of a trigate and one or several GAAs. A vertical space Hspace = 8 nm is kept constant in between the NWs unless mentioned otherwise. The value is in accordance with cleanroom developments and the thickness of the HKMG layers (§3).
Concerning the doping levels, intrinsic silicon channels only are used for the simulations. Source and drain are heavily doped with 1023 atoms/cm3 and can be considered metallic – low access resistance – which emphasizes the junction and channel intrinsic resistances. Vertical junction lines are located under the spacer at Lspacer/2. As explained in the third chapter (§3), RSD are in-situ doped. The activation anneal that follows distributes the dopants from the RSD uniform reservoirs to the intrinsic channel following the Gaussian distribution pictured in Figure 2.5 according to Fick’s diffusion law.
GAA structure confines the electric field within the channel: there is no need to simulate more than one NW in this configuration and the total output current can be obtained by multiplying by the number of channels. In other words, the normalized current does not depend on the number of channels, only on their geometry. This effect was verified with a few experiments on trigate devices and FinFETs. This helps saving precious simulation time. This is a consequence of having uniform and very high doping of the S/D region, allowing to neglect the problematic of S/D access resistance and to focus on the intrinsic architectures themselves. In future work, models including doping non-uniformity and more realistic concentrations will have to be added. However, it is possible to imagine that SNWFET technology could benefit from the same state-of-the-art than FinFETs as their fabrication process and their dimensions are very close (§3).
Figure 2.5 – Gaussian distribution of dopants in the channel: source-drain longitudinal-section of a GAA nanowire device with LG = 16 nm and LSpacer = 4.2 nm.

Electrostatic and carrier transport models

The present chapter focuses on the electrostatic behavior of FinFETs and SNWFETs which dominates their performance. Carrier transport is described with a Drift-Diffusion model based on Boltzmann semi-classical transport. A constant mobility of 100 cm²/V.s and a saturation velocity of 1.07×107 cm/s are set along with a supply voltage VDD = 0.7 V. As a consequence of this carrier transport model, no quantitative projection can be realized, especially concerning the above threshold current. Subsequently, the results presented in this chapter evidence mostly the differences in electrostatics under threshold.
Quantum confinement effects in such narrow structures must be considered. The density-gradient model proposed by [Ancona 1989] includes this effect inside a Drift-Diffusion approach thanks to a calibration of the parameters previously obtained in [Pons 2013]. The computation of Poisson-Shrodinger is then avoided and quantum effects are simulated through the charge density thanks to a correction of the potential. In the present conditions, Pons et al. calibration is valid down to W = HNW = 6 nm. Consequently, the simulated channels have been restricted to fin widths larger than 7 nm and NW thicknesses higher than 6.33 nm. A channel cross-section is presented in Figure 2.6 where the difference in between a classical model and a density gradient model can be observed. The quantum correction shifts the pic of carrier concentration from the interface by a distance so called the dark space (DS).

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Intrinsic delay approximation

The intrinsic delay can be approximated using the effective current Ieff in the expression (Eq. 2-1) according to [Wei 2011 TED]. Ieff is defined by equations (Eq. 2-2) to (Eq. 2-4). In the present case, the extraction is realized at +VDD = 0.7 V from the gate voltage VG0 required to reach the fixed off state current IOFF = 100 nA/µm (for high performance applications: this value has been defined in ITRS 2013). This is intended to suppress the effect of threshold voltage variation in between the different architectures in comparison with an extraction at fixed gate voltage.
Figure 2.7 illustrates the extraction of Ieff according to the equations (Eq. 2-2) to (Eq. 2-4). VG0 is extracted on the ID-VG curve at VD = VDD = 0.7 V, and consequently, the off current IOFF,VD=VDD/2 considered for the extraction of IH in the ID-VG plot at VD = VDD/2 is lower than 100 nA/µm depending on DIBL.

Parasitic capacitances – inverter equivalent capacitance

The equivalent capacitance Ceq for an inverter as defined in [Wei 2011 TED] is reported in equations (Eq. 2-5) to (Eq. 2-7) with M = 2 the Miller Effect in an inverter and FO = 3 the fan-out number. Therefore, Ceq is a combination of all the parasitic capacitances illustrated in Figure 2.8.
with M = 2 the coefficient for Miller effect, FO = 3 the electric fan-out, Weff the effective width – or device perimeter – tinv the inversion layer thickness and Cgd0 the gate-to-drain parasitic capacitance extracted at VG = 0 V and VD = 0 V. Another capacitance is added to take into account the effect of the back-end: CBE = 2 fF is a common value used internally for the back-end capacitance.
This derivation simplifies the computation of the intrinsic delay since only the 0 V gate-to-drain parasitic capacitance needs to be extracted from the simulation and not the entire C-V plot. This is in accordance with the level of precision needed for this preliminary study as well as with the basic mobility model employed.

Table of contents :

1. Need of 3D-channels in CMOS technology
1.1. Physics of multi-gate devices: scaling length volume inversion & mobility.
1.1.1. CMOS scaling.
1.1.2. Double gate device physics: volume inversion
1.1.3. Multi-gate device physics: carrier transport in thin films.
1.1.4. Conclusion
1.2. Double-gate devices: from FDSOI and FinFET to nanowires
1.2.1. FDSOI
1.2.2. Horizontal Double-gate devices
1.2.3. Silicon-On-Nothing (SON)
1.2.4. Vertical double-gate: towards FinFET
1.2.5. Conclusions
1.3. The nanowire technology: down to the end of the roadmap?
1.3.1. Tri-Gates, π-gate, Ω-gate and gate-all-around (GAA) nanowire FETs
1.3.2. Technology boosters: channel orientation and strain in trigate nanowire FETs.
1.3.3. Technology boosters: the case of Sidewall Image Transfer (SIT)
1.3.4. Stacked NWs
1.3.5. Conclusion and thesis proposal
2. Benchmarking Stacked Nanowires Technologies with FinFET
2.1. TCAD Model: Simulation Parameters and Extraction
2.1.1. TCAD model
2.1.2. Intrinsic delay approximation
2.1.3. Parasitic capacitances – inverter equivalent capacitance
2.2. Electrostatics of 3D-architectures
2.2.1. Subthreshold behavior
2.2.2. Parasitic capacitances
2.2.3. Conclusion
2.3. Constant footprint and height comparison using TCAD simulation
2.3.1. Comparison guidelines
2.3.2. Results and discussion
2.3.3. Towards stacked nanosheets?
2.4. Internal spacer and gate alignment is key to reduce parasitic capacitances
2.5. Discussions
2.6. Conclusion
3. Stacked nanowire FETs: integration challenges and process optimization.
3.1. Gate last integration flows of stacked nanowires
3.1.1. NW Last: polysilicon sacrificial gate
3.1.2. NW First: HSQ sacrificial gate
3.1.3. Alternatives?
3.1.4. Conclusion
3.2. Si/SiGe superlattice
3.3. Si/SiGe fins patterning
3.4. SiGe selective removal
3.5. Source and drains (S/D) and internal spacers fabrication
3.5.1. Surface preparation
3.5.2. Selective epitaxial growth (SEG)
3.5.3. S/D in a NW last approach with aligned internal spacers.
3.5.4. S/D in a NW first approach with self-aligned internal spacers
3.6. Electron beam lithography of HSQ
3.6.1. Conditions
3.6.2. Layouts description
3.6.3. Resist developing
3.6.4. Observations
3.6.5. Limitation and perspectives
3.7. Chemical mechanical planarization (CMP)
3.7.1. Introduction to CMP
3.7.2. Polysilicon sacrificial gate CMP (NW Last approach)
3.7.3. Sacrificial gate opening CMP
3.7.4. Metal CMP (NW Last & NW First)
3.8. Conclusion
4. Achieved integrations and optimization perspectives
4.1. Electrical characterization of SNWFETs fabricated in a NW last approach
4.1.1. Device fabrication
4.1.2. Electrical measurements
4.2. 3D SAC and STI: HSQ the ultimate resist?
4.2.1. SNWFETs fabricated in a NW first approach
4.2.2. Alternative approach with HSQ sacrificial gates and lateral insulation
General Conclusion

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